EP0588613A2 - Circuits de protection de batterie - Google Patents

Circuits de protection de batterie Download PDF

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Publication number
EP0588613A2
EP0588613A2 EP93307267A EP93307267A EP0588613A2 EP 0588613 A2 EP0588613 A2 EP 0588613A2 EP 93307267 A EP93307267 A EP 93307267A EP 93307267 A EP93307267 A EP 93307267A EP 0588613 A2 EP0588613 A2 EP 0588613A2
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EP
European Patent Office
Prior art keywords
battery
state
terminal
power down
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP93307267A
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German (de)
English (en)
Other versions
EP0588613B1 (fr
EP0588613A3 (en
Inventor
Yasuhito C/O Intellectual Property Div. Eguchi
Kanji C/O Intellectual Property Div. Murano
Akira C/O Sony Energytec Inc. Sanpei
Hajime Tamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Motorola Solutions Japan Ltd
Original Assignee
Sony Corp
Nippon Motorola Ltd
Motorola Japan Ltd
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Application filed by Sony Corp, Nippon Motorola Ltd, Motorola Japan Ltd filed Critical Sony Corp
Publication of EP0588613A2 publication Critical patent/EP0588613A2/fr
Publication of EP0588613A3 publication Critical patent/EP0588613A3/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H02J7/0014—Circuits for equalisation of charge between batteries
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H7/00—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions
    • H02H7/18—Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for batteries; for accumulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0029—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits
    • H02J7/0031—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with safety or protection devices or circuits using battery or load disconnect circuits

Definitions

  • the present invention relates to battery protection circuits for protecting secondary batteries from overcharge and overdischarge.
  • a protection circuit is provided to prevent the battery from being deteriorated.
  • batteries can be protected from the overcharge and the overdischarge by turning on and/or off a battery charger detecting the overcharge and the overdischarge and the load side of the batteries on the basis of a total voltage of the batteries connected in series.
  • a battery protection function is not provided on the battery side but is provided on the battery charger and the load side thereof.
  • the battery protection circuit additionally includes a circuit for turning on and/or off the power supply by detecting a temperature by a thermostat or the like incorporated within the battery or battery pack when an abnormal overcharge or overcurrent is caused in the charger or load side.
  • This previously-proposed battery protection circuit is such one that a rechargeable power apparatus having a rapid chargeable secondary battery includes an overdischarge preventing mechanism and an overcharge preventing function by constructing a discharging circuit and a charging circuit by using a device including therein a parasitic diode.
  • a MOS FET metal oxide semiconductor field effect transistor
  • a charging and discharging circuit in the process in which secondary batteries connected in series are repeatedly charged and discharged, even when a battery capacity balance is lost by a difference of individual batteries, includes a battery capacity balance circuit having a function to recover such balance to thereby prevent the battery from being overcharged and overdischarged.
  • the battery capacity balance circuit is fundamentally formed of a circuit for protecting the battery.
  • this battery capacity balance circuit is comprised of circuit groups for detecting the overcharge, turning off the charging current, detecting the overflow, detecting the overdischarge, turning off the discharge current, and detecting the hysteresis and the overcurrent to protect the battery.
  • a battery protection circuit which comprises a secondary battery, state detecting means for detecting a voltage of the secondary battery and detecting an overdischarged or overcharged state of the secondary battery by comparing the detected voltage with a reference voltage, first switching means for interrupting a discharging current, second switching means for interrupting a charging current, control means for controlling the switching of the first and second switching means on the basis of a detected result of the state detecting means, power down switching means for interrupting a voltage and a reference voltage supplied to the state detecting means, power down means for making the power down switching means nonconductive when the overcharged state of the secondary battery is detected by the state detecting means, power down releasing means for returning the power down switching means from nonconductive state to a conductive state when a charging of the secondary battery is started again from the overdischarged state, and state holding means for detecting that the secondary battery is started to be charged again from the overdischarged state by detecting a charging voltage produced across terminals of the secondary battery
  • a battery protection circuit wherein the state holding means holds the charging state until a voltage of the secondary battery gets away from an overdischarging region.
  • a battery protection circuit wherein the power down means makes the power down switching means nonconductive when an overdischarged state of at least one secondary battery is detected by the state detecting means in a battery protection circuit in which a plurality of secondary batteries are connected in series.
  • a battery protection circuit wherein the power down releasing means makes a reference voltage power down switching means in the state detecting means conductive first and makes other power down switching means conductive after the occurrence of a reference voltage is detected.
  • a battery protection circuit which further comprises means for forcing the secondary battery to set in the state so that the secondary battery can be charged when the power down switching means is nonconductive and a voltage of the secondary battery is substantially OV.
  • a battery protection circuit which further comprises power down inhibiting means for holding the power down switching means in conductive state when any of the secondary batteries is in the overcharged state.
  • a battery protection circuit which further comprises overcurrent detecting means for detecting a large current when the large current is flowed momentarily, in which the power down inhibiting means hold the power down switching means in the conductive state on the basis of a detection signal from the overcurrent detecting means.
  • the overcharge state and the overdischarged state are detected by monitoring a voltage from each of batteries constructing a battery pack and a switch, a load, a battery charger on the battery pack side are turned on and/or off, an influence exerted by abnormality of the battery charger or the load can be suppressed to the minimum.
  • the batteries forming the battery pack can be balanced in response to the overcharged state or overdischarge state.
  • a current consumed by the circuit group used in detecting and controlling the voltage is set in the power down mode in the overdischarging region to thereby reduce a consumed current.
  • FIG. 1 of the accompanying drawings schematically shows in block form a battery protection circuit according to a first embodiment of the present invention.
  • a battery protection circuit that is generally depicted by reference numeral 1 in FIG. 1 comprises a detecting unit 2, a control unit 3, a restoring unit 4, a power down switching (SW) unit 5 and a charge and discharge switching unit 6.
  • the battery protection circuit 1 is adapted to control the charge and discharge of batteries Abat and Bbat which are a plurality of batteries.
  • the detecting unit 2 is comprised of a battery voltage detecting unit 7 and an overcurrent detecting unit 8.
  • the battery voltage detecting unit 7 is adapted to detect the overcharge state (A, B) and the overdischarge state (A, B) from respective voltages of the batteries Abat and Bbat.
  • the overcurrent detecting unit 8 is adapted to detect the overcurrent state.
  • the control unit 3 is comprised of a discharge system control logic unit 9, a discharge switching (Sw) control unit 10, a ground (GND) level shift unit 11, a charge system control logic unit 12 and a charge SW control unit 13.
  • the discharge-system control logic unit 9 and the discharge SW control unit 10 of the control unit 3 are adapted to output an overflow current signal to the battery voltage detecting unit 7, the discharge switch signal to the charge and discharge switching unit 6 which will be described later on and a power down signal to the restoring unit 4 on the basis of the charge and discharge states of the batteries Abat and Bbat detected by the battery voltage detecting unit 7 of the detecting unit 2 and the overcurrent signal state detected by the overcurrent detecting unit 8.
  • a ground signal from the discharge system control logic unit 9 and the discharge SW control unit 10 is input through the GND level shift unit 11 to the charge system control logic unit 12 and the charge SW control unit 13.
  • the GND level shift unit 11 of the control unit 3 is adapted to determine ground potentials to be constant because grounds of the discharge switches of the discharge system control logic unit 9 and the discharge SW control unit 10 and charge switches of the charge system control logic unit 12 and the charge SW control unit 13 are different.
  • the charging system control logic unit 12 and the charging SW control unit 13 of the control unit 3 control the charging and discharging switching unit 6 and output a power down releasing signal to the restoring unit 4 on the basis of the battery condition and a charging detection (activating circuit) or the like.
  • the restoring circuit 4 is comprised of a power down control unit 14 and an activating circuit charging detecting unit 15.
  • the power down control unit 14 supplies a power down signal from the discharging system control logic unit 9 to the power down SW unit 5 which will be described later on and also supplies the power down releasing signal from the charging system control logic unit 12 to the power down SW unit 5. Further, the activation circuit charging detecting unit 15 automatically starts the charging of the secondary battery.
  • the power down SW unit 5 supplies the power down signal from the power down control unit 14 to the detecting unit 2 and the control unit 3 and turns off the power supply to set the battery protecting circuit in the power down mode.
  • the charging and discharging switch 6 charges and discharges batteries Abat and Bbat under the control of the discharging SW control unit 10 and the charging SW control unit 13 of the control unit 3.
  • the battery voltage detecting unit 7 of the detecting unit 2 constantly monitors the discharging state of the batteries Abat and Bbat.
  • an overdischarge signal A or overdischarge signal B is supplied to the discharging system control logic unit 9 of the control unit 3 so that, under the control of the discharging system control unit 9, the discharging switch of the charging and discharging switching unit 6 is turned off by the discharging SW control unit 10.
  • the discharging switch 6 in the charging and discharging switching unit 6 is turned off and also the battery protection circuit is placed in the power down mode.
  • the battery protection circuit is placed in the power down mode when any one of the batteries Abat and Bbat is set in the overdischarged state, i.e., when any one of the batteries Abat and Bbat in the battery formed of the batteries Abat and Bbat is set in the overdischarged state.
  • the discharging switch of the charging and discharging switching unit 6 is turned off by the discharging SW control unit 10 of the control unit 3. Incidentally, if an overcurrent state presented by a momentary large current falls within a predetermined period of time, the discharging switch is not turned off. Further, if the overdischarging state presented by the large current falls within a predetermined time, the battery protection circuit can be prevented from being placed in the power down mode.
  • the overcharge signal A or B is supplied to the charging system control logic unit 12 of the control unit 3 and the charging switch of the charging and discharging switching unit 6 is turned off. Simultaneously, the battery that had been overcharged is discharged by an overflow circuit, though not shown.
  • the charging operation is forcibly carried out on the basis of the charging detecting signal from the activation circuit charging detecting unit 15 of the restoring unit 4 under the control of the charging SW control unit 13 of the control unit 3 and also, a power down mode releasing preparation is carried out. Then, a total battery voltage is increased in excess of a predetermined voltage value (reference voltage is generated), whereby the detecting unit 2 is forced in the power down releasing mode to detect the battery voltage.
  • the power down release signal is supplied to the power down control unit 14 of the restoring unit 4 and the battery protection circuit is released from the power down mode.
  • the battery is escaped from the overdischarged state and set in the normal charged state.
  • the battery protection circuit is not set in the power down mode and the overcharged state is given a highest priority.
  • a discharging characteristic of battery formed of batteries Abat and Bbat and the power down mode will be described.
  • the battery voltage is continuously lowered with a discharging time while drawing a discharge curve 16, and the condition that the battery voltage becomes less than an overdischarge voltage 17 that is set to a predetermined voltage value in advance is the overdischarged state.
  • the detecting unit 2 shown in FIG. 1 detects the overdischarged state, then the discharge for the load is stopped by turning off the discharging switch of the charging and discharging switching unit 6. Then, battery voltage is held in an overdischarge region 18 and a remaining capacity (mAh) 19 thereof shown hatched can be calculated beforehand.
  • the power down mode is proposed, which is a method of interrupting the supply of a current to circuits except necessary minimum circuits of the battery protection circuit that was set in the overdischarged state.
  • the discharging curve becomes a discharging direction curve 21 so that a voltage maintaining period provided by the remaining capacity 19 when the battery protection circuit 1 is set in the overdischarged state becomes very different as compared with the voltage maintaining period in which the power down mode is not provided.
  • FIG. 3 (formed of FIGS.- 3A, 3B drawn on two sheets of drawings so as to permit a suitably large scale) is a block diagram showing a circuit arrangement of the battery protection circuit 1.
  • the battery protection circuit 1 is mainly comprised of five comparators, a plurality of switching elements and a plurality of gates that are connected as described below.
  • a battery assembly in which the battery protection circuit 1 is incorporated is connected to a plus side of the battery Abat through a fuse 23 connected to a plus side connection terminal (Eb+) that is connected to the plus side of a battery charger or the load.
  • the minus side of the battery Abat is connected to the plus side of the battery Bbat, presenting a sc-called series connection.
  • the minus side of the battery Bbat is connected through a discharging power NMOS transistor QD and a charging - power NMOS transistor QC to the minus side terminal (Eb-) that is the connection terminal of the minus-side of the battery charger or the load.
  • the battery protection circuit 1 is connected through the plus-side terminal (Eb+) and a protection resistor R10 to a terminal VDD.
  • a terminal CPU is connected through a resistor R11 to a drain terminal of an NMOS transistor Q14.
  • a junction between the minus-side of the battery Abat and the plus-side of he battery Bbat is connected to a terminal VC.
  • a minus-side terminal CPD of the battery Bbat is connected through a resistor 12 to a drain terminal of an NMOS transistor Q15 and also connected through a protection resistor R13 to a terminal VSS.
  • the power N-channel MOS transistor QD (hereinafter referred to as a power NMOS transistor QD) is a transistor which includes a source terminal, a gate terminal, a drain terminal and a parasitic diode D1.
  • the source terminal thereof is connected to the minus-side of the battery Bbat, the gate terminal thereof is connected to a terminal DO, and the drain terminal thereof is connected to the drain terminal of the power NMOS transistor QC.
  • the power N-channel MOS transistor QC (hereinafter referred to as a power NMOS transistor QC) is a transistor which includes a source terminal, a gate terminal, a drain terminal and a parasitic diode D2.
  • the source terminal thereof is connected to the minus-side terminal (Eb-)
  • the gate terminal thereof is connected to a terminal OV
  • the drain terminal thereof is connected to the drain terminal of the power NMOS transistor QD.
  • the minus-side terminal (Eb-) is connected to a terminal VM through a protection resistor R22.
  • Power down switches PDSW1 to PDSW4 are closed and opened by power down signals PDA, PDB.
  • One terminals of the power down switches PDSW1, PDSW2 are connected to the terminal VDD.
  • a junction a of the power down switch PDSW1 and a junction b of the power down switch PDSW2 which are other terminals are connected to power supply terminals of comparators COMP1, COMP2, COMP3, COMP4, COMP5 and a power supply terminal of a reference voltage source 29, respectively.
  • One terminal of the power down switch PDSW3 is connected to the other end of a resistor R16 and the other terminal thereof is connected to the terminal VC.
  • One terminal of the power down switch PDSW4 is connected to the other end of the resistor R19 and the other terminal thereof is connected to the terminal VSS.
  • the comparator COMP1 comprises two input terminals and one output terminal.
  • One inverting input terminal (hereinafter referred to as minus-side input terminal) thereof is connected to a junction between the other end of a resistor R14 and one end of a resistor R15 and the other non-inverting input terminal (hereinafter referred to as a plus-side input terminal) thereof is connected to the plus-side of a reference voltage E1 (+1.5V).
  • the output terminal thereof is connected to one input terminal of a NOR gate G2.
  • one end of the resistor R14 is connected to the terminal VDD and the other end of the resistor R15 is connected to a junction between one end of the resistor R11 and the plus-side input terminal of the comparator COMP2.
  • the minus side of the reference voltage E1 is connected to the terminal VC.
  • the comparator COMP2 comprises two input terminals and one output terminal. One minus-side input terminal thereof is connected to the plus side of the reference voltage E1 (+1.5V) and the other plus-side input terminal thereof is connected to a junction between the other end of the resistor R15 and one end of the resistor R16. The output terminal thereof is connected to one input terminal of a NOR gate G8 and the gate terminal of the NMOS transistor Q14. A hysteresis switch input terminal of the comparator COMP2 is connected to the output terminal of an AND gate G1.
  • the comparator COMP3 comprises two input terminals and one output terminal. One minus-side input terminal thereof is connected to a junction between the other end of a resistor R17 and one end of a resistor R18. The other plus-side input terminal thereof is connected to a plus-side of a reference voltage E2 (+1.5V). The output terminal thereof is connected to the other input terminal of the NOR gate G2. One end of the resistor R17 is connected to the terminal VC and the other end of the resistor R18 is connected to one end of the resistor R19 and the plus-side input terminal of the comparator COMP4.
  • the comparator COMP4 comprises two input terminals and one output terminal. One minus-side input terminal thereof is connected to a plus side of the reference voltage E2 (+1.5V) and the other plus-side input terminal thereof is connected to a junction between the other end of the resistor R18 and one end of the resistor R19. The output terminal thereof is connected to the other input terminal of the NOR gate G8 and the gate terminal of the NMOS transistor Q15. A hysteresis switch input terminal of the comparator COMP4 is connected to the output terminal of the AND gate G1.
  • a comparator COMP5 comprises two input terminals and one output terminal. One minus-side input terminal thereof is connected to the plus side of a reference voltage E3 (+0.4V) and the other plus-side input terminal thereof is connected to the terminal VM. The output terminal thereof is connected to the other end of a resistor R4 that constructs a delay CR and one input terminal of the AND gate G1. One end of the resistor R4 is connected to one input terminal of a NOR gate G9 and one end of a capacitor C2. The other end of the capacitor C2 is connected to the terminal VDD.
  • the AND gate G1 includes two input terminals and one output terminal. One input terminal thereof is connected to the output terminal of the comparator COMP5, and the other input terminal thereof is connected to the output terminal of the NOR gate G2. The output terminal of the AND gate G1 is connected to the hysteresis switch input terminals of the comparators COMP2, COMP4.
  • the NOR gate G2 includes two input terminals and one output terminal. One input terminal thereof is connected to the output terminal of the comparator COMP1, and the other input terminal thereof is connected to the output terminal of the comparator COMP3.
  • the output terminal of the AND gate G2 is connected to the other input terminal of the AND gate 1, one input terminal of the NOR gate G3, one input terminal of a NOR gate G11 and the gate terminal of an NMOS transistor Q13.
  • the NOR gate G3 includes two input terminals and one output terminal. One input terminal thereof is connected to the output terminal of the NOR gate G2, and the other input terminal thereof is connected to the output terminal of the comparator COMP5. The output terminal of the AND gate G3 is connected to one input terminal of a NAND gate G4 and the other input terminal of the NOR gate G9.
  • the NAND gate G4 includes two input terminals and one output terminal. One input terminal thereof is connected to the output terminal of the NOR gate G3, and the other input terminal of the NAND gate G4 is connected to the output terminal of the NOR gate G8. The output terminal of the NAND gate G4 is connected to one input terminal of a NAND gate G6 of a power down latch circuit.
  • a NAND gate G5 includes two input terminals and one output terminal and forms the power down latch circuit together with the NAND gate G6.
  • One input terminal of the NAND gate G5 is connected to the other end of a resistor R1, and the other input terminal thereof is connected to the output terminal of the NAND gate G6.
  • the output terminal of the NAND gate G5 is connected to the source terminal of an NMOS transistor Q11.
  • a power down signal PDB is generated from this output terminal of the NAND gate G5.
  • the NAND gate G6 includes two input terminals and one output terminal, and forms the power down latch circuit together with the NAND gate G5.
  • One input terminal of the NAND gate G6 is connected to the output terminal of the NAND gate G5 and the other input terminal of the NAND gate G6 is connected to the output terminal of the NAND gate G4.
  • the output terminal of the NAND gate G6 is connected to the input terminal of the NAND gate G5, an input section of a GND level shift unit LSH1 of a charging logic, and one input terminal of a NOR gate G11.
  • An OR gate G7 includes two input terminals and one output terminal and is one element of the charging logic.
  • One input terminal of the NAND gate G6 is connected through the resistor R1 to the terminal VDD and the other input terminal is connected to an output section of the GND level shift unit LSH1.
  • the output terminal thereof is connected to one input terminal of a NAND gate G10.
  • the NOR gate G8 includes two input terminals and one output terminal. One input terminal thereof is connected to the output terminal of the comparator COMP2, and the other input terminal thereof is connected to the output terminal of the comparator COMP4. The output terminal thereof is connected to the input terminal of the NAND gate G4, and an input section of a GND level shift unit LSH2 which constructs the charging logic.
  • the NOR gate G9 includes two input terminals and one output terminal. One input terminal thereof is connected to the output terminal of the NOR gate G3, and the other input terminal thereof is connected to one end of the resistor R4 and one end of the capacitor C2. The output terminal thereof is connected through the terminal DO to the gate terminal of the power NMOS transistor QD.
  • the NAND gate G10 includes two input terminals and one output terminal. One input terminal thereof is connected to the output terminal of the OR gate G7, and the other input terminal thereof is connected to the output section of the GND level shift unit LSH2. The output terminal thereof is connected to the gate terminals of PMOS transistors Q9, Q10.
  • the NOR gate G11 includes two input terminals and one output terminal. One input terminal thereof is connected to the output terminal of the NOR gate G2, and the other input terminal thereof is connected to the output terminal of an NMOS transistor Q12. The output terminal thereof is connected to the gate terminal of the NMOS transistor Q12.
  • the P-channel MOS transistor Q9 (hereinafter referred to as a PMOS transistor Q9) includes a source terminal, a gate terminal and a drain terminal.
  • the source terminal thereof is connected to the terminal VDD
  • the gate terminal thereof is connected to the output terminal of the NAND gate G10
  • the drain terminal thereof is connected to the drain terminal of the NMOS transistor Q10 and to the gate terminal of the power NMOS transistor QC through the terminal OV.
  • the N-channel MOS transistor Q10 (hereinafter referred to as an NMOS transistor Q10) includes a source terminal, a gate terminal and a drain terminal.
  • the source terminal thereof is connected to the terminal VM and the GND of the charging logic, and the gate terminal thereof is connected to the output terminal of the NAND gate G10.
  • the drain terminal thereof is connected to the drain terminal of the PMOS transistor Q9 and to the gate terminal of the power NMOS transistor QC through the terminal OV.
  • the P-channel MOS transistor Q11 (hereinafter referred to as a PMOS transistor Q11) includes a source terminal, a gate terminal and a drain terminal.
  • the source terminal thereof is connected to the output terminal of the NAND gate G5, the gate terminal thereof is connected to the reference voltage source 29 at its terminal from which a reference voltage generation signal is generated and the drain terminal thereof is connected to one end of the resistor R0.
  • the power down signal (PDA) is generated from this drain terminal. Incidentally, the other end of the resistor R0 is grounded.
  • the N-channel MOS transistor Q12 (hereinafter referred to as an NMOS transistor Q12) includes a source terminal, a gate terminal and a drain terminal.
  • the source terminal thereof is connected to the terminal VM
  • the gate terminal thereof is connected to the output terminal of the NOR gate G11
  • the drain terminal thereof is connected to the input terminals of the NAND gates G5, G7 and the other end of the resistor R1.
  • the N-channel MOS transistor Q13 (hereinafter referred to as an NMOS transistor Q13) includes a source terminal, a gate terminal, and a drain terminal.
  • the source terminal thereof is connected to the terminal VSS
  • the gate terminal thereof is connected to the output terminal of the NOR gate G2
  • the drain terminal thereof is connected to one end of a resistor R5.
  • the other end of the resistor R5 is connected to the terminal VM.
  • the N-channel MOS transistor Q14 (hereinafter referred to as an NMOS transistor Q14) includes a source terminal, a gate terminal and a drain terminal.
  • the source terminal thereof is connected to the terminal VC
  • the gate terminal thereof is connected to the output terminal of the comparator COMP2
  • the drain terminal thereof is connected through the resistor R11 to the terminal CPU.
  • the N-channel MOS transistor Q15 (hereinafter referred to as an NMOS transistor Q15) includes a source terminal, a gate terminal and a drain terminal.
  • the source terminal thereof is connected to the terminal VC
  • the gate terminal thereof is connected to the output terminal of the comparator COMP4
  • the drain terminal thereof is connected through the resistor R12 to the terminal CPD.
  • the input section of the GND level shift unit LSH1 is connected to the output terminal of the NAND gate G6 of the power down latch circuit and the output section thereof is connected to the input terminal of the 0R gate G7.
  • the input section of the GND level shift unit LSH2 is connected to the output terminal of the NOR gate G8, and the output section thereof is connected to the input terminal of the NAND gate G10.
  • the reference voltage source 29 generates reference voltage values E1, E2 and E3.
  • the reference voltage value E1 is supplied to the plus-side input terminal of the comparator COMP1 and the minus-side input terminal of the comparator COMP2.
  • the reference voltage value E2 is supplied to the plus-side input terminal of the comparator COMP3 and the minus-side input terminal of the comparator COMP4.
  • the reference voltage value E3 is supplied to the minus-side input terminal of the comparator COMP5.
  • the overcharged state or overdischarged state is detected by comparing the reference voltages El, E2 (+1.5V) and so-called detection voltage values generated through rudder resistor groups (R14, R15, R11, R17, R18, R19) by the comparators COMP1 to COMP4. More specifically, the comparators COMP1, COMP3 compare detection voltage values that result from dividing the voltages of the batteries Abat, Bbat with the positive reference voltages E1, E2 (+1.5V) supplied to the plus-side input terminals thereof.
  • the comparators COMP2, COMP4 compare detection voltage values that result from dividing the voltages of the batteries Abat, Bbat with the positive reference voltages E1, E2 (+1.5V) supplied to the minus-side input terminals thereof.
  • the reference voltage El (+1.5V) holds the potential of the terminal VC at zero V by the level shift and supplies the same to the comparators COMP1, COMP2 as comparison reference voltages.
  • the rudder resistor groups formed of the resistors R14, R15, R11, R17, R18, R19 connected in series are provided so as to divide voltages so that these divided voltages can be compared with the reference voltages El, E2 (+1.5V) upon overcharge and upon overdischarge. Further, the comparator COMP5 is utilized to detect an overcurrent by comparing the reference voltage value E3 (+1.5V) with the voltage at the minus-side terminal (Eb-1).
  • a charging current is flowed to the minus-side terminal (Eb-) from the plus-side terminal (Eb+) serving as the connection terminal connected to the external battery charger or the discharge load terminal through the secondary batteries Abat, Bbat and the power NMOS transistors QD, QC.
  • a H (high) level signal from the overcharge detecting circuit (comparators COMP2, COMP4) is input to the NOR gate G8.
  • the output from the NOR gate G8 becomes an L (low) level signal.
  • This L level signal is input to the GND level shift unit LSH2 of the charging logic, in which it is ground level shifted (which will be described later on). At that time, the input condition of the NAND gate G10 are not satisfied any more, and the power NMOS transistor QC is turned off.
  • the comparators COMP2, COMP4 have enough hysteresis width voltage (e.g., 0.2V). When the hysteresis signal from the AND gate G1 is at H level, the hysteresis is released (see (e) Hysteresis signal which will be described later on), and operation for starting the recharging is avoided immediately.
  • the H level signal from the output terminal of the comparator COMP2 turns on the NMOS transistor Q14, whereby an overcharging overflow current is discharged to protect the battery Abat serving as the battery. More specifically, when the NMOS transistor Q14 is turned on, a current is flowed to the resistor R11 through the terminal CPU connected to the plus-side of the battery Abat, and the battery Abat is discharged to the low voltage (e.g., 4.2V) corresponding to the hysteresis width.
  • the comparator COMP4 and the PMOS transistor Q15 or the like utilized in the battery Bbat similarly function and therefore need not be described.
  • the hysteresis circuit is operated so as to avoid the immediate charging after the charging current was interrupted and the overcharged overflow current is discharged, thereby protecting the batteries (batteries Abat, Bbat).
  • the batteries (batteries Abat and Bbat) are set in the discharging state by connecting the load to the plus-side terminal (Eb+) and the minus-side terminal (Eb-).
  • This discharging state is constantly monitored by the overdischarge detecting circuit mainly formed of the comparators COMP1, COMP3.
  • the comparator COMP1 that detects the overdischarged state of the battery Abat will be described hereinafter.
  • the H level signal from the output terminal of the comparator COMP1 is input through the NOR gate G2 to the NOR gate G3 which derives the H level signal.
  • the H level signal from the NOR gate G3 is input to the NOR gate G9 whose output signal goes to L level to turn off the power NMOS transistor QD, thereby interrupting the discharge current.
  • the H level signal from the NOR gate G3 is input to the NAND gate G4 and an L level signal is input to the NAND gate G6 of the power down latch circuit.
  • the L level signal is set in the latched state by the NAND gates G5, G6.
  • the power down signal (PDB) goes to the L level.
  • the power down signal (PDA) also is set in the L level by means of the PMOS transistor Q11.
  • the power down signal (PDB) that is set in the L level opens the power down switch PDSW2 to interrupt the reference voltage source 29, thereby turning off the reference voltage sources E1, E2, E3.
  • the power down signal (PDA) that is set in the L level opens the powder down switches PDSW2, PDSW3, PDSW4 to interrupt the voltages supplied to the comparators COMP1 to COMP5 and voltages supplied to the rudder resistor groups (resistors R14, R15, R11, R17, R18, R19).
  • the circuit arrangement Upon power down, the circuit arrangement is switched such that the outputs of the comparators COMP2, COMP4 become L level signals, the outputs of the comparators COMP1, COMP3 become H level signals, the output of the comparator COMP5 becomes the L level signal and the output of the delay CR becomes the H level signal.
  • the overcurrent is detected by a circuit arrangement mainly formed of the comparator COMP5 and detected by comparing the overcurrent with the reference voltage value E3 (+0.4V).
  • the signal developed at the output terminal of the comparator COMP5 goes to H level.
  • the H level signal from the output terminal of the comparator COMP5 becomes an L level signal through the NOR gate G9 after a duration (e.g., about 1.8 msec) generated from the delay CR formed of the resistor R4 and the capacitor C2.
  • This L level signal turns off the power NMOS transistor QD to interrupt the discharging current.
  • a high voltage at the terminal (Eb+) becomes the voltage value at the terminal VM through loads connected between the plus-side terminal (Eb+) and the minus-side terminal (Eb-). Accordingly, the high voltage value generated at the terminal VM becomes a value substantially close to the voltage value generated at the plus-side terminal (Eb+) so that the overcharge detection signal at the output side of the comparator COMP5 can be held at the H level.
  • the overcurrent detection signal at the output terminal of the comparator COMP5 becomes L level so that the protection circuit can be returned from the overcurrent state.
  • the delay CR formed of the resistor R4 and the capacitor C2 is given a time longer than a predetermined time (e.g., about 1.8 msec). This time is provided in order to prevent the power NMOS transistor QD from being turned off when a large current is momentarily flowed due to a capacitor load or the like.
  • the power down inhibiting logic is formed of the NOR gate G3 and the NAND gate G4 and a circuit that can inhibit the protection circuit from being set in the power down mode when the overdischarge is generated by the momentary large current or the like.
  • a current large enough that the overcurrent detection is started it is frequently observed that a voltage is lowered to the overdischarge detection state by the inside resistance of the battery.
  • the battery protection circuit is set in the power down mode by the capacitor a load or short-circuited erroneously. Therefore, the comparator COMP5 is operated such that, when the H level signal is output from the output terminal thereof, such H level signal is immediately input to the NOR gate G3 to thereby inhibit the battery protection circuit from entering the power down mode.
  • the battery protection circuit is inhibited from entering the power down mode by the NAND gate G4. Accordingly, when the battery is set in the overflow discharge state, the power supply is turned off, thereby preventing the battery from being left in the overcharged state.
  • the power NMOS transistor QC When the battery is discharged under the overcharged state (e.g., immediately after the battery was charged), the power NMOS transistor QC is in its OFF state so that the discharging current is flowed to the parasitic diode D2. Then, the voltage at the terminal VM is increased by the forward voltage (e.g., about 0.7V) of the parasitic diode D2, whereby the overcurrent detecting circuit is actuated to inhibit the battery from being discharged.
  • the forward voltage e.g., about 0.7V
  • the H level signal is forcibly input to the hysteresis releasing circuit of the comparators COMP2, COMP4 to forcibly release the hysteresis.
  • the overcharge detection is returned to the normal state and the power NMOS transistor QD is turned on, thereby making it possible to discharge the battery.
  • the AND gate G1 inhibits the hysteresis from being released.
  • the discharging current cannot be flowed. Therefore, when the hysteresis is released, the battery protection circuit is set in the power down mode. At that time, the overflow current of the overcharged battery Abat or Bbat is turned off. The reason that the hysteresis is inhibited from being released is to avoid the battery from being left in the overcharged state, thereby protecting the battery. It is a very rare case that one battery is overcharged while the other battery is overdischarged.
  • the battery charger When the battery charger is connected between the plus-side terminal (Eb+) and the minus-side terminal (Eb-), a charging voltage is applied across the two terminals so that the charging voltage becomes higher than the battery voltage (voltage between the batteries Abat and Bbat). As a result, the voltage at the minus-side terminal (Eb-) becomes lower than the minus-side voltage (GND) of the battery Bbat.
  • the power NMOS transistor QD and the power NMOS transistor QC are both in their OFF states as described before.
  • the input to the NAND gate G5 goes to the L level signal so that the output of the NAND gate G5 becomes the H level signal regardless of the state of the other input. Accordingly, the power down releasing can be prepared (see (g) Return from the power down mode which will be described later on).
  • the NMOS transistor Q12 When the NMOS transistor Q12 is turned on, the PMOS transistor Q9 is turned on and the NMOS transistor Q10 is turned off through the OR gate G7 and the NAND gate G10. Then, the potential at the terminal 0V becomes equal to the potential at the plus-side terminal (Eb+) through the terminal VDD to turn on the power NMOS transistor QC, thereby the charging being started to flow a charging current.
  • the output of the NOR gate G11 becomes the H level signal to cause the signal at the gate terminal of the NMOS transistor Q12 to go to H level. Accordingly, the activation states can be held by the NMOS transistor Q12 and the NOR gate G11.
  • the gate voltage of the power NMOS transistor QC is 0V and the source voltage thereof, i.e., voltage at the terminal VM is minus voltage and the power NMOS transistor QC is turned on and hence a charging current is flowed thereto.
  • the power NMOS transistor QD is in its OFF state so that the charging current is flowed through the parasitic diode D1 of the power NMOS transistor QD.
  • the GND level of the charging logic is at the potential of the terminal VM, a voltage corresponding to a voltage drop generated by the charging in the power NMOS transistors QD, QC becomes a voltage source that drives the charging logic.
  • the gate voltage of the power NMOS transistor QC is increased and the minus voltage of the potential of the terminal VM is decreased.
  • the power NMOS transistor QD is turned on and the potential at the terminal VM becomes substantially 0V.
  • both signals at the output terminals of the comparators COMP1, COMP2 become L level signals. Further, the signal at the output terminal of the NOR gate G2 becomes the H level signal and the signal to the input terminal of the NAND gate G6 becomes the H level signal. On the other hand, because the signal to the input terminal of the NAND gate G5 is the L level signal, the output of the NAND gate G5 becomes the H level signal.
  • the two input signals to the NAND gate G6 become the H level signals so that the latch in the power down circuit is inverted and the circuit is escaped from the power down mode.
  • the output of the NOR gate G2 becomes the H level signal so that the input signal to the AND gate G11 becomes the H level signal. Regardless of the level of the other input signal to the NAND gate G11, the output from the NAND gate G11 becomes the L level signal. At that time, the holding of the activation state by the NMOS transistor Q12 and the NAND gate G11 is released.
  • the power NMOS transistor QD is turned on through the NOR gate G9 by the L level signal developed at the output terminal of the NOR gate G3 and the charging in the normal state is presented.
  • the normal charging state can be returned from the power down mode when the power down signals PDA and PDB are changed from the L level to the H level.
  • the condition that the power down signal PDA goes to H level is deeply associated with the voltage of the battery (batteries Abat, Bbat). That is to say, the power down signal PDA controls the rudder resistor groups and on and/or off of the comparators.
  • the power down signal PDB controls the on and/or off of the reference voltage source 29.
  • the power down signal PDB is immediately returned to the H level when the charging is started (NMOS transistor Q12 is turned on and the PMOS transistor Q11 is turned off), thereby closing the power down switch PDSW2 to turn on the reference voltage source 29.
  • the PMOS transistor Q11 When the reference voltage values El, E2 (+1.5V) and E3 (0.4V) are generated, the PMOS transistor Q11 is turned on by a predetermined reference voltage generation signal and the power down signal PDA goes to L level, thereby closing the power down switches PDSW1, PDSW3, PDSW4.
  • the signal of L level from the activation circuit (formed of the NOR gate G11 and the NMOS transistor Q12) is input to the OR gate G7 whose output signal goes to H level.
  • This H level signal is input to one input terminal of the NAND gate G10.
  • the NAND gate 10 is supplied at the other input terminal with the signal from the GND level shift unit LSH2.
  • the H level signal so that the output of the NAND gate G10 becomes the L level signal.
  • the PMOS transistor Q9 is turned on and the NMOS transistor Q10 is turned off.
  • the signal at the terminal OV becomes the H level signal and the power NMOS transistor QC is turned on, thereby flowing the charging current.
  • the signal from the overcharge detecting circuit goes to H level.
  • This H level signal is input to the NAND gate G10 by means of the ground level shift (will be described later on) and the H level signal is output at the output terminal of the NAND gate G10. Then, the signal at the terminal OV becomes the L level signal and the power NMOS transistor QC is turned off, thereby interrupting the charging current.
  • the ground level shift will be described with reference to FIGS. 4 and 5.
  • a source potential of the power NMOS transistor QD that is a discharging side ground (potential of the ground terminal VSS of the battery) and a potential of the source terminal of the high power NMOS transistor QC that is a charging side ground (potential of the terminal VM) are shifted to become the same potential.
  • FIG. 4 shows a charging and discharging circuit mainly formed of the power NMOS transistor QD and the power NMOS transistor QC in the aforementioned circuit arrangement shown in FIGS. 3A and 3B.
  • the charging power NMOS transistor QC and the discharging power NMOS transistor QD cannot be turned off completely unless the voltages thereof are set to 0V relative to the potential of the terminal VM and the potential of the terminal VSS.
  • FIG. 5 shows an example of the ground level shift in which the MOS transistors in the charging logic shown in FIG. 3 are represented by QP, QN and the resistor R.
  • the MOS transistor QP is turned on and the MOS transistor QN is turned off so that an OUT signal goes to H level without causing any trouble. If the potential of the terminal VM is lowered (always lowered during the charging) without interposing the resistor R between the MOS transistors QP and QN, the MOS transistor QN also is turned on. Hence, the MOS transistors QP and QN are both turned on. That is, the short-circuited state is presented and hence the H level state of the OUT signal becomes the level of the indefinite state. Further, there is then the disadvantage that a short-circuit current is flowed between the MOS transistors QP and QN.
  • the resistor R is interposed between the MOS transistors QP and QN. With this arrangement, even when the MOS transistor QN is turned on, a signal at a point y goes to L level and the H level state of the OUT signal is maintained. Since the short-circuit current is flowed to the resistor R, the resistance value of the resistor R must be selected in a range of from several kilohms to several megohms. Incidentally, the short-circuit current is flowed only when the battery is charged. Further, when the a signal at the point x is at H level, even if the potential at the terminal VM is decreased or increased, then the OUT signal goes to L level (i.e., potential at the terminal VM).
  • the outputs of the respective comparators are separated and set in the necessary signal states. That is to say, the signal of the overcharge detection signal is maintained at L level, the signal of the overdischarge detection output is maintained at H level and the signal of the overcurrent detection output is maintained at L level.
  • the NMOS transistor Q13 in the constant current circuit is a circuit that makes the voltage at the terminal VM zero V when a load is not applied.
  • resistors R10, R11, R12, R13 and R22 connected to the terminals VDD, CPU, CPD, VSS and VM are protection resistors and a potential difference due to the resistors is not generated fundamentally.
  • the battery protection circuit embodying the invention can achieve the following effects.
  • the battery protection circuit includes the state holding means for detecting by the occurrence of the charging voltage across the terminals of the secondary battery that the battery is changed to the re-charging starting state from the overdischarging state and holding the charging state, the battery protection circuit can be returned from the so-called power down mode to the charging state with ease.
  • the state holding means can reliably return the circuit from the power down mode by holding the charging state until the voltage of the secondary battery is escaped from the overcharge region.
  • the circuit can be reliably returned from the power down mode by making the power down switching means conductive after the reference voltage is generated.
  • the battery protection circuit includes forcing means for forcing the secondary battery to become chargeable if the voltage of the secondary battery is substantially 0V when the power down switching means is nonconductive, the circuit can be returned from the power down mode without a voltage that controls the switching means.
  • the battery protection circuit includes the power down inhibiting means for inhibiting the power down switching means nonconductive when any one of the secondary batteries is overcharged, a so-called overflow current of the secondary battery in the overcharged state can be flowed and the life of battery can be extended.
  • the battery protection circuit includes the preventing means for preventing the circuit from being set in the power down mode when a large current is flowed momentarily, the circuit can be prevented from being placed in the power down mode even when a large current momentarily generated by the load of the capacitor occurs or when the momentary short-circuit state occurs. Therefore, the battery voltage can be supplied stably regardless of temporarily external fluctuation.
EP93307267A 1992-09-17 1993-09-15 Circuits de protection de batterie Expired - Lifetime EP0588613B1 (fr)

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JP274945/92 1992-09-17
JP27494592A JP3291530B2 (ja) 1992-09-17 1992-09-17 バッテリー保護回路

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EP0588613A2 true EP0588613A2 (fr) 1994-03-23
EP0588613A3 EP0588613A3 (en) 1994-09-28
EP0588613B1 EP0588613B1 (fr) 1998-02-04

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EP (1) EP0588613B1 (fr)
JP (1) JP3291530B2 (fr)
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DE69316812T2 (de) 1998-05-20
EP0588613B1 (fr) 1998-02-04
KR100298248B1 (ko) 2001-10-24
KR940008213A (ko) 1994-04-29
JPH06104015A (ja) 1994-04-15
JP3291530B2 (ja) 2002-06-10
DE69316812D1 (de) 1998-03-12
EP0588613A3 (en) 1994-09-28
US5493197A (en) 1996-02-20

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