EP0000897B1 - Verfahren zum Herstellen von lateral isolierten Siliciumbereichen - Google Patents

Verfahren zum Herstellen von lateral isolierten Siliciumbereichen Download PDF

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Publication number
EP0000897B1
EP0000897B1 EP78100614A EP78100614A EP0000897B1 EP 0000897 B1 EP0000897 B1 EP 0000897B1 EP 78100614 A EP78100614 A EP 78100614A EP 78100614 A EP78100614 A EP 78100614A EP 0000897 B1 EP0000897 B1 EP 0000897B1
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EP
European Patent Office
Prior art keywords
approximately
silicon
grooves
etching
layer
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Expired
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EP78100614A
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German (de)
English (en)
French (fr)
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EP0000897A1 (de
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James Allan Bondur
Hans Bernhard Pogge
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/131—Reactive ion etching rie
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/161—Tapered edges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/168—V-Grooves
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Definitions

  • the invention relates to a method for producing laterally insulated areas in a silicon body, in which grooves at the locations at which the insulation frame is to be formed are etched into the silicon by means of reactive ion etching, then thermally oxidized on the surface and then filled with dielectric material, wherein the dielectric material with the necessary thickness is applied to the entire surface of the silicon body in order to planarize the surface above the groove, and finally the dielectric material is etched away outside the grooves.
  • the dielectric materials that have been used are silicon dioxide, glass, etc.
  • the preferred isolation for these active devices and circuits is any type of dielectric isolation.
  • the dielectric isolation has a significant advantage over the isolation by means of a P / N junction in that it allows the circuit elements to abut the isolation, which enables a greater packing density of the active and passive components on the chip with the integrated circuits.
  • a kind of dielectric insulation includes the formation of grooves or depressions at the locations in the silicon where the isolation areas are to be formed.
  • the usual protective film consists of a double layer made of silicon nitride and silicon dioxide.
  • the "Vogeischn thereby" is a non-planar structure made of silicon dioxide, at the upper edge of the groove, and is caused by the lateral oxidation of the silicon under the silicon nitride layer. Because in the oxidation of silicon. the silicon dioxide formed takes up about twice the space, and since the silicon nitride limits the unrestricted expansion of the resulting oxide material, the silicon nitride is pushed upwards at the edge of the groove. Finally, mechanical stresses in the immediate vicinity of the groove also result from this phenomenon. Difficulties in subsequently producing diffusion-doped regions which directly abut the vertical part of the silicon dioxide. Because of this difficulty in direct bumping, there is no substantial benefit hoped for by the silica area. This method described above is described more fully and in more detail in U.S. Patents 3,970,486, 3,534,234 and 3,648,125 and in German Patent Application No. 22 18 892.
  • an epitaxial layer is very much dependent on the area ratio of silicon dioxide regions to silicon regions.
  • the semiconductor material would grow at different speeds on two silicon regions which are of different sizes, so that at the end of the method step the epitaxial layer in these regions is of different thickness.
  • mesa structures there is also a tendency to form crystallographic facets. This results in a pyramid-like growth and leads to a widening of the isolation areas, which cannot be corrected using lithographic means.
  • the sloped interface between the silicon and the silica also makes it difficult to reliably cause diffused areas to collide with the silica area.
  • the method according to the invention it is possible to fill the grooves with an insulating material which has a high dielectric constant and a high density and has no interfering inclusions. This is essentially achieved in that the grooves taper with the depth in a fixed manner, which enables the grooves to grow practically unhindered by the geometry.
  • an upper surface of the dielectric material in the grooves is obtained which is essentially coplanar with the surface of the silicon body.
  • the planarity of the structure produced facilitates the production of reliable, very tightly packed integrated circuits.
  • the procedure is advantageously such that a reactive gas is used which consists of a halogen consists of the group chlorine, bromine, iodine or a material containing one of these elements and is added to the reaction atmosphere in amounts in the range between about 2 and about 10%, that worked at a pressure in the range between about 2.66 and about 66 ⁇ bar and the etch rate to a value in the range between about 0.03 and 0.08 ⁇ m / min. is set.
  • etching takes place at a power density in the range between approximately 0.1 and approximately 0.75 W / cm 2 .
  • the method according to the invention is also particularly advantageous when a silicon body is used which contains at least one highly doped layer and the grooves are etched so deep that they essentially penetrate the highly doped layer. If such a highly doped layer is present, it is difficult, even with reactive ion etching, to avoid severe undercutting in the lateral direction, which poses problems when a particularly high packing density of the semiconductor components is required. A particularly slight undercut is obtained if chlorine is used as the reactive gas when carrying out the process according to the invention and this is admixed in amounts between about 2 and about 8% of the reaction atmosphere.
  • a photoresist mask formed in accordance with the desired pattern of the grooves is produced in a known manner on the SiO 2 layer applied to the silicon body in order to produce a defined taper angle and if the SiO layer is then reactively etched so that the etching speed ratio from Si0 2 to photoresist is approximately one.
  • the taper angle is understood to mean the angle which the side wall of a groove which tapers with the depth forms with the vertical.
  • mask windows are obtained which taper with the depth.
  • openings are then obtained whose side walls have a taper angle in the range between approximately 5 and approximately 20 °.
  • the dielectric material used for filling the grooves is generated by chemical vapor deposition and deposited in a thickness in the range between approximately 1 and approximately 5 ⁇ m the minimum thickness required for the planarization is determined as a function of the width of the groove at the upper edge and if the dielectric material outside the grooves is removed by means of reactive ion etching.
  • the grooves extend into a P-type area, it is advantageous to prevent inversion to implant impurities which impart P-conductivity in an amount in the bottom areas of the grooves prior to thermal oxidation in such an amount that a region of P + - type arises.
  • FIG. 1A includes the monocrystalline silicon substrate 10, which for illustration purposes is designated as belonging to the P type, an N + type layer 12 applied to the substrate 10 and one applied to the layer 12 Layer 14 with an N conductivity.
  • the invention is also applicable to all or some of the layers 10, 12 and 14 would be of a conductivity type opposite to that indicated.
  • layer 12 preferably consists of a region with high conductivity so that it can take over the function of the collector of a bipolar transistor in the final structure. This structure can be created using various manufacturing processes.
  • the preferred technique is to start from a single-crystal P-type silicon substrate and then to introduce an impurity, for example arsenic, antimony or phosphorus, which produces an N-type conductivity, over the entire surface into the silicon substrate by means of diffusion or ion implantation.
  • an impurity for example arsenic, antimony or phosphorus
  • a layer of the N + type can be produced in which the surface concentration of the impurity is in the range between approximately 1 ⁇ 10 19 and 1 ⁇ 10 21 atoms / cm 3 .
  • Layer 14 is then grown on layer 12 by epitaxy. This can be done using known methods, for example, by allowing mixtures of SiCL 4 and H 2 or SiH 4 and H 2 to act on the substrate at temperatures in the range between about 1000 and about 1200 ° C.
  • the N + type layer has a typical thickness in the range between about 1 and 3 ⁇ m, while the epitaxial layer has a thickness in the range between about 0.5 and 10 ⁇ m, the exact thickness of the component to be manufactured , depends.
  • the structure could be produced using various combinations of thermal diffusion, ion implantation and / or epitaxial growth.
  • highly doped buried areas or layers are not necessary and can therefore be omitted. This applies, for example, to FET components.
  • a multiplicity of buried, highly doped regions of different doping types can be produced by means of a multiplicity of epitaxy and diffusion process steps. These structures could be needed for both buried sub-collectors and buried lines.
  • FIG. 1A and 1B process steps relate to the etching of openings or channels in the silicon structure, which taper with the depth, by means of reactive ions.
  • a silicon dioxide layer 16 is produced by known methods, ie either by means of thermal growth at a temperature of 970 ° C. in a wet or dry oxygen atmosphere or by means of chemical precipitation from the vapor phase. Other mask materials such as silicon nitride or aluminum oxide or combinations of these materials etc. can also be used.
  • the openings 18 are created in the oxide layer in the areas in which dielectric insulation is desired. These openings are created using standard photolithography and etching techniques.
  • the structure shown in FIG. 1A has now been prepared for the etching process using reactive ions.
  • the high-frequency excited plasma as stated in the above-mentioned publication, consists of a material containing reactive chlorine, bromine or iodine.
  • the thickness of the masking layer 16 is in the range between approximately 0.2 and 2 ⁇ m, the exact thickness depending on the required depth of the hole or groove to be produced in the silicon.
  • the precise description of the high-frequency discharge device is given in the aforementioned publication.
  • the atmosphere during reactive ion etching or the plasma atmosphere preferably consists of a combination of an inert gas, such as argon, with a material containing chlorine.
  • a power density in the order of about 0.1 to 0.75 W / cm 2 generated by means of a high-frequency voltage source causes a reactive ion etching of the silicon, in which the silicon is removed at a speed in the range between about 0.02 and about 0.08 ⁇ m per minute becomes.
  • the desired etch result is shown in FIG. 1B, which shows that the openings or channels at least partially penetrate the P conductivity type region 10. In any case, the channels or openings largely pass through the region 12 of the N + type.
  • the openings or channels taper at least so much in depth that the angle between the opening wall and the vertical is greater than about 2 °. This is necessary because in the subsequent process step of filling with dielectric material, the deposition near the upper edge of the groove takes place somewhat more quickly than at the bottom of the groove. If one assumed holes or grooves with vertical walls, the narrow hole still present would eventually grow near the upper edge of the hole during the deposition, with the result that the dielectric material in the area under the overgrown area bad quality. In the case of a groove that tapers to a sufficient extent with the depth, the groove is filled from its bottom.
  • the preferred degree of taper which is suitable for a suitable filling with dielectric material, such as silicon dioxide, by means of chemical vapor deposition, becomes partly what 6 will become clear depend on the groove width.
  • a taper angle which is greater than 20 °, takes up an unnecessarily large area on the surface of the semiconductor component. This formation of the structure with the tapering grooves or holes depends mainly on two factors. The first factor is the angle of the side wall of the opening 18 in the masking layer 16. The second factor is the difference in the speeds at which the mask material and the substrate material are etched. The higher the ratio of the speeds at which the substrate material and the mask material are etched, the more vertical the hole walls in the silicon substrate become.
  • openings are generally obtained in the photoresist, which taper somewhat with the depth. Then, when the reactive ion etching is used to create openings in the underlying silicon dioxide film through the tapered windows in the photoresist, and when the ratio of the speed of the lacquer etching to that of the silicon dioxide etching is approximately one, the tapering present in the lacquer window is applied to the window in the Transfer silica. As a result, this taper is then transferred to the silicon unless a high ratio of the silicon etching speed to that of the silicon dioxide etching is set.
  • the taper in the silicon dioxide mask is preferably in the taper angle range between 5 and 20 °.
  • the windows in the silicon dioxide will also have vertical perforated walls and it is the case under these conditions that the openings in the silicon will practically also have vertical perforated walls, regardless of the ratio of the speed of silicon etching to the speed of silicon dioxide etching.
  • etch rates also affects the undercutting of highly doped N + or P-type areas, such as area 12.
  • etch rates of approximately 0.07 ⁇ m per minute holes with vertical lines are formed in N + type areas Walls without lateral undercut.
  • Fig. 2 is a graph showing the influence of the silicon etching rate in ⁇ m per minute depending on the percentage of the chlorine-containing material in the argon for various pressures in the reaction chamber.
  • Curve 20 shows the conditions at a pressure of 13.33 ⁇ bar. At this pressure and at the stated etching speeds, there is practically no undercutting in the N + type regions, it being irrelevant what the percentage of the chlorine-containing material is.
  • curve 20 shows that when the content of the chlorine-containing material in argon changes from 10% to about 3%, the taper angle in the holes changes from about 0 to about 20 °.
  • the power is 0.16 W / cm 2 and the cathode consists of silicon dioxide.
  • Curve 22 shows that a groove with vertical walls is obtained at an etching speed of 0.06 ⁇ m per minute and a chlorine content in argon of approximately 3%. If one moves upwards on the curve to an etching rate of 0.10 ⁇ m per minute and a content of the chlorine-containing material in argon of 5%, one can see the undercut in the area of the N + type.
  • Curve 24 shows the situation at a pressure of 53.33 ⁇ bar. With a content of 2% in the chlorine-containing material in argon and an etching rate of 0.06 ⁇ n per minute, undercutting in the N + range is not a problem. However, if you move up the curve up to an etching speed of 0.08 ⁇ m, the undercut begins to become clear. It can be assumed that if you move further up the curve, the undercutting becomes even stronger. At point 26, the ratio is shown at a total pressure of 119.99 ⁇ bar.
  • the main problem that arises from underetching the N + region is that it limits the minimum distance that two insulation regions can have from each other. If a very strong undercut occurs and two isolation areas are very close together, the area 14 will fully undercut. In addition, the N + collector region will be completely removed so that no transistor can be formed. Yet another problem will arise in each undercut area in that the non-linear tapered holes are not clean with dielectric, chemical Precipitated material, such as silicon dioxide, which is deposited from the vapor phase. The result is a filled groove that contains a buried hole or channel.
  • the openings or channels are thermally oxidized by exposing the semiconductor body to an oxidizing atmosphere, for example a moist oxygen atmosphere at 970 ° C.
  • the semiconductor body is exposed to the atmosphere for between about 10 and about 30 minutes to create the preferred silicon dioxide thickness within the opening or channel.
  • the preferred thickness is between about 0.05 and about 0.2 microns.
  • the purpose of the thermal oxide 30 is to ensure good properties of the interface between the silicon and the silicon dioxide. Dielectric material that has been applied by chemical vapor deposition generally does not have as good properties as thermally grown oxide. Dielectric material with good properties is necessary in order to allow diffused P / N junctions to subsequently hit the dielectric insulation.
  • the minimum thickness must be nominally 0.05 fl m in order to have a good thermal silicon dioxide layer. A thinner layer could cause difficulties in having through pores in the oxide and could cause problems with electrical integrity.
  • the maximum thickness is mainly determined by the time it takes to grow at elevated temperatures. Long growth times at high temperatures mean that every diffused P / N junction moves in the silicon regions. Very thick oxide films that have been produced at such temperatures also cause stress problems in the silicon material.
  • the thermally grown oxide 30 follows the tapering of the side walls of the opening, which has been produced by means of reactive ion etching, almost exactly.
  • the result of the next process step, in which the openings are filled with a suitable dielectric material, is shown in FIG. 1 D, from which it can be seen that the opening or the channel has a layer consisting of silicon dioxide produced by vapor deposition 32 is filled.
  • the preferred filling process is a chemical deposition of silicon dioxide from the vapor phase at 800 to 1000 ° C using gas mixtures which contain CO 2 , SiH 4 and N 2 or N 2 0, SiH 4 and N 2 .
  • Typical deposition rates are between 5 and 10 nm / min. and the total thickness of the deposited layers is nominally 3 fL m for 2 ⁇ m wide grooves if an approximately planar surface is desired.
  • the specific relationship between the flatness and the thickness of the silica deposited by chemical vapor deposition is shown in FIG. 8.
  • FIGS. 3, 4 and 5 show the crucial importance of the taper angle of the hole side walls and the hole dimensions on the silicon surface.
  • 3 shows a narrow filling gap 40 in the middle part of the openings filled with silicon dioxide deposited by chemical vapor deposition. This filling gap can only be seen after etching a cross section through the channel filled with SiO z .
  • the formation of the filling gap causes an oxide with poor properties in this area and experiments show that the gap is formed by the silicon dioxide being covered by openings which are narrower than 0.2 ⁇ m and whose taper angle is less than 20 ° Lochs grows over.
  • FIGS. 3, 4 and 5 illustrate the progressive filling of the grooves by means of a series of lines which represent the same layer thickness ranges from silicon dioxide deposited by chemical vapor deposition.
  • the fill gap 40 tends to be buried further down in the filled groove as the groove width widens and the taper angle increases.
  • Fig. 4 shows the influence of the taper angle using grooves of the same width.
  • the final step of the process is reactive ion etching of the silicon dioxide layer 32 shown in FIG. 1D, producing the structure shown in FIG. 1.
  • the excess of the silica is conveniently removed by reactive ion etching and with the aid of an optical film thickness measurement system, or if the rate at which the silica is etched is known, even without such a system.
  • the device used for this process step preferably consists of a device for sputter etching at low pressure, in which the plate is positioned on a cathode cover plate made of silicon.
  • a fluorinated hydrocarbon such as CF 4 can be used as the etchant because then the ratio of the speed of SiO etching to that of Si etching is approximately 1: 1.
  • the gas pressure can be in the range between 13.33 and 93.3 ⁇ bar and the gas flow in the range between 2 and 50 ccm / min.
  • the high-frequency power level is preferably in the range between approximately 0.1 and 0.5 W / cm 2 .
  • the result of thinning the silicon dioxide layer by means of reactive ion etching may make the insufficiently buried area of poor oxide visible in the center of the groove. This is a potential problem because any wet etch of the wafer surface, if such areas of poor silica are exposed, would cause a gap to form in that area. Such gaps could become potential traps for dirt or process residues, and could negatively affect the properties of the component.
  • An alternative method to circumvent some of the undercutting problems would be to fabricate a highly doped region 12 in such a way that this region is interrupted or has recesses where the openings or channels are to be formed. In this case, a weakly doped region of the P type would surround the region which is to be etched by means of reactive ions.
  • This alternative requires special oxidation, photolithography and etching steps so that this area of the N + type with recesses is created.
  • Forming a P + -type region below the isolation region can be useful if the substrate is P-type. In such cases, the P region tends to change its resistance, which can go so far as to invert the material from which it is thermally oxidized into an N-type one.
  • a P + area prevents such an inversion possibility.
  • Such a region can be created by introducing a dopant, such as boron, by means of ion implantation before the thermal oxidation of the groove. The best way to do the ion implantation is to cover the groove with a thin layer of silicon dioxide produced by chemical vapor deposition.
  • Such a covering between approximately 50 and 80 nm thick allows implantation of, for example, boron through the bottom of the groove into the silicon but not through the silicon dioxide on the side walls of the groove. This is because the ion beam forms an acute angle with the side walls of the groove and therefore the distance through the silicon dioxide to the silicon is greater than the real thickness of the silicon dioxide.
  • Another possibility of modifying the fabrication process is to subject the semiconductor substrates to a tempering step in a water vapor atmosphere after the process step in which the structure shown in FIG. 1E is formed.
  • This tempering which is carried out at a temperature in the range between 900 and 950 ° C. any poor quality exposed silica in the central region of the groove is converted to good quality silica.
  • the advantage of this process modification is that when it is used it is no longer so important that the areas of poor quality silica are buried with certainty and it is therefore no longer so important that the taper angles are as large as possible, which is why it is possible to provide a higher component density in the manufacture of integrated circuits.
  • With the process modification it is possible, for example, to convert poor-quality silicon dioxide, which has arisen when there are small taper angles, such as those in the range between 2 and 4 °, into good-quality ones.
  • the method according to the invention is not restricted to the applications described in the exemplary embodiments.
  • the single-crystalline silicon regions produced by means of the described method can also be used to form components other than bipolar transistors.
  • Such components would be passive components such as Resistors and active components such as Include metal oxide silicon field effect transistors (MOSFET) devices.
  • MOSFET include metal oxide silicon field effect transistors

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EP78100614A 1977-08-15 1978-08-07 Verfahren zum Herstellen von lateral isolierten Siliciumbereichen Expired EP0000897B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US824361 1977-08-15
US05/824,361 US4104086A (en) 1977-08-15 1977-08-15 Method for forming isolated regions of silicon utilizing reactive ion etching

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EP0000897A1 EP0000897A1 (de) 1979-03-07
EP0000897B1 true EP0000897B1 (de) 1981-12-23

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US (1) US4104086A (enrdf_load_stackoverflow)
EP (1) EP0000897B1 (enrdf_load_stackoverflow)
JP (1) JPS5432277A (enrdf_load_stackoverflow)
CA (1) CA1097826A (enrdf_load_stackoverflow)
DE (1) DE2861453D1 (enrdf_load_stackoverflow)
IT (1) IT1112298B (enrdf_load_stackoverflow)

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US4140558A (en) * 1978-03-02 1979-02-20 Bell Telephone Laboratories, Incorporated Isolation of integrated circuits utilizing selective etching and diffusion
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DE2861453D1 (en) 1982-02-11
CA1097826A (en) 1981-03-17
JPS6220696B2 (enrdf_load_stackoverflow) 1987-05-08
US4104086A (en) 1978-08-01
JPS5432277A (en) 1979-03-09
IT1112298B (it) 1986-01-13
IT7826393A0 (it) 1978-08-02

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