DE68927852T2 - Verfahren zur Herstellung von Gräben mit abgerundeter Unterseite in einem Siliziumsubstrat zur Herstellung von Isolationen für Grabenstrukturen - Google Patents

Verfahren zur Herstellung von Gräben mit abgerundeter Unterseite in einem Siliziumsubstrat zur Herstellung von Isolationen für Grabenstrukturen

Info

Publication number
DE68927852T2
DE68927852T2 DE68927852T DE68927852T DE68927852T2 DE 68927852 T2 DE68927852 T2 DE 68927852T2 DE 68927852 T DE68927852 T DE 68927852T DE 68927852 T DE68927852 T DE 68927852T DE 68927852 T2 DE68927852 T2 DE 68927852T2
Authority
DE
Germany
Prior art keywords
producing
silicon substrate
trench structures
trenches
insulation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68927852T
Other languages
English (en)
Other versions
DE68927852D1 (de
Inventor
Pierluigi Crotti
Nadia Iazzi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Application granted granted Critical
Publication of DE68927852D1 publication Critical patent/DE68927852D1/de
Publication of DE68927852T2 publication Critical patent/DE68927852T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/944—Shadow
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/978—Semiconductor device manufacturing: process forming tapered edges on substrate or adjacent layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
DE68927852T 1988-12-15 1989-12-06 Verfahren zur Herstellung von Gräben mit abgerundeter Unterseite in einem Siliziumsubstrat zur Herstellung von Isolationen für Grabenstrukturen Expired - Fee Related DE68927852T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8883689A IT1225636B (it) 1988-12-15 1988-12-15 Metodo di scavo con profilo di fondo arrotondato per strutture di isolamento incassate nel silicio

Publications (2)

Publication Number Publication Date
DE68927852D1 DE68927852D1 (de) 1997-04-17
DE68927852T2 true DE68927852T2 (de) 1997-06-19

Family

ID=11323815

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68927852T Expired - Fee Related DE68927852T2 (de) 1988-12-15 1989-12-06 Verfahren zur Herstellung von Gräben mit abgerundeter Unterseite in einem Siliziumsubstrat zur Herstellung von Isolationen für Grabenstrukturen

Country Status (5)

Country Link
US (1) US5068202A (de)
EP (1) EP0375632B1 (de)
JP (1) JPH02214140A (de)
DE (1) DE68927852T2 (de)
IT (1) IT1225636B (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1243919B (it) * 1990-11-20 1994-06-28 Cons Ric Microelettronica Procedimento per l'ottenimento di solchi submicrometrici planarizzati in circuiti integrati realizzati con tecnologia ulsi
US5290396A (en) 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5248625A (en) 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
US5354706A (en) * 1993-03-02 1994-10-11 Lsi Logic Corporation Formation of uniform dimension conductive lines on a semiconductor wafer
GB9410874D0 (en) * 1994-05-31 1994-07-20 Inmos Ltd Semiconductor device incorporating an isolating trench and manufacture thereof
KR0151051B1 (ko) * 1995-05-30 1998-12-01 김광호 반도체장치의 절연막 형성방법
WO1997006558A1 (en) * 1995-08-09 1997-02-20 Advanced Micro Devices, Inc. Process for rounding corners in trench isolation
KR0171733B1 (ko) * 1995-08-28 1999-03-30 김주용 반도체 소자의 콘택홀 형성 방법
DE69725245T2 (de) * 1996-08-01 2004-08-12 Surface Technoloy Systems Plc Verfahren zur Ätzung von Substraten
GB9616225D0 (en) 1996-08-01 1996-09-11 Surface Tech Sys Ltd Method of surface treatment of semiconductor substrates
US6187685B1 (en) 1997-08-01 2001-02-13 Surface Technology Systems Limited Method and apparatus for etching a substrate
US6132631A (en) * 1997-08-08 2000-10-17 Applied Materials, Inc. Anisotropic silicon nitride etching for shallow trench isolation in an high density plasma system
US5998301A (en) * 1997-12-18 1999-12-07 Advanced Micro Devices, Inc. Method and system for providing tapered shallow trench isolation structure profile
US6004864A (en) * 1998-02-25 1999-12-21 Taiwan Semiconductor Manufacturing Company Ltd. Ion implant method for forming trench isolation for integrated circuit devices
US6096612A (en) * 1998-04-30 2000-08-01 Texas Instruments Incorporated Increased effective transistor width using double sidewall spacers
US6001704A (en) * 1998-06-04 1999-12-14 Vanguard International Semiconductor Corporation Method of fabricating a shallow trench isolation by using oxide/oxynitride layers
US6110793A (en) * 1998-06-24 2000-08-29 Taiwan Semiconductor Manufacturing Company Method for making a trench isolation having a conformal liner oxide and top and bottom rounded corners for integrated circuits
US6107206A (en) * 1998-09-14 2000-08-22 Taiwan Semiconductor Manufacturing Company Method for etching shallow trenches in a semiconductor body
US6417013B1 (en) 1999-01-29 2002-07-09 Plasma-Therm, Inc. Morphed processing of semiconductor devices
US6521959B2 (en) * 1999-10-25 2003-02-18 Samsung Electronics Co., Ltd. SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same
US6580150B1 (en) * 2000-11-13 2003-06-17 Vram Technologies, Llc Vertical junction field effect semiconductor diodes
KR100392894B1 (ko) * 2000-12-27 2003-07-28 동부전자 주식회사 반도체 소자의 트렌치 형성 방법
KR100846385B1 (ko) * 2002-07-19 2008-07-15 주식회사 하이닉스반도체 반도체 소자의 트렌치형 소자분리막 형성방법
US6586314B1 (en) * 2002-10-08 2003-07-01 Chartered Semiconductor Manufacturing Ltd. Method of forming shallow trench isolation regions with improved corner rounding
KR100943481B1 (ko) 2002-12-30 2010-02-22 동부일렉트로닉스 주식회사 이이피롬 셀의 제조방법
US7531367B2 (en) * 2006-01-18 2009-05-12 International Business Machines Corporation Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit
US20090127722A1 (en) * 2007-11-20 2009-05-21 Christoph Noelscher Method for Processing a Spacer Structure, Method of Manufacturing an Integrated Circuit, Semiconductor Device and Intermediate Structure with at Least One Spacer Structure
KR101435520B1 (ko) 2008-08-11 2014-09-01 삼성전자주식회사 반도체 소자 및 반도체 소자의 패턴 형성 방법
KR101540083B1 (ko) 2008-10-22 2015-07-30 삼성전자주식회사 반도체 소자의 패턴 형성 방법
JP5558480B2 (ja) * 2008-10-31 2014-07-23 アプライド マテリアルズ インコーポレイテッド Ｐ３ｉチャンバにおける共形ドープの改善
US8158522B2 (en) * 2009-09-25 2012-04-17 Applied Materials, Inc. Method of forming a deep trench in a substrate
CN112259453A (zh) * 2020-10-22 2021-01-22 绍兴同芯成集成电路有限公司 一种对芯片表面开槽的方法及芯片
CN116053261B (zh) * 2023-01-28 2023-06-20 微龛(广州)半导体有限公司 高精度的薄膜电阻装置及其制备方法

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NL170348C (nl) * 1970-07-10 1982-10-18 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een tegen dotering en tegen thermische oxydatie maskerend masker wordt aangebracht, de door de vensters in het masker vrijgelaten delen van het oppervlak worden onderworpen aan een etsbehandeling voor het vormen van verdiepingen en het halfgeleiderlichaam met het masker wordt onderworpen aan een thermische oxydatiebehandeling voor het vormen van een oxydepatroon dat de verdiepingen althans ten dele opvult.
JPS5228550B2 (de) * 1972-10-04 1977-07-27
US4271583A (en) * 1980-03-10 1981-06-09 Bell Telephone Laboratories, Incorporated Fabrication of semiconductor devices having planar recessed oxide isolation region
JPS5856437A (ja) * 1981-09-30 1983-04-04 Toshiba Corp 半導体装置の製造方法
US4472873A (en) * 1981-10-22 1984-09-25 Fairchild Camera And Instrument Corporation Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure
FR2529714A1 (fr) * 1982-07-01 1984-01-06 Commissariat Energie Atomique Procede de realisation de l'oxyde de champ d'un circuit integre
JPS59202648A (ja) * 1983-05-02 1984-11-16 Oki Electric Ind Co Ltd 半導体装置の製造方法
US4538343A (en) * 1984-06-15 1985-09-03 Texas Instruments Incorporated Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking
USH204H (en) * 1984-11-29 1987-02-03 At&T Bell Laboratories Method for implanting the sidewalls of isolation trenches
US4666555A (en) * 1985-08-23 1987-05-19 Intel Corporation Plasma etching of silicon using fluorinated gas mixtures
JPS63152155A (ja) * 1986-12-16 1988-06-24 Sharp Corp 半導体装置の製造方法
DE3865058D1 (de) * 1987-02-24 1991-10-31 Sgs Thomson Microelectronics Isolationsverfahren mit einer durch eine schutzschicht aus oxid geschuetzten zwischenschicht.
US4942137A (en) * 1989-08-14 1990-07-17 Motorola, Inc. Self-aligned trench with selective trench fill

Also Published As

Publication number Publication date
EP0375632A2 (de) 1990-06-27
US5068202A (en) 1991-11-26
JPH02214140A (ja) 1990-08-27
EP0375632B1 (de) 1997-03-12
IT1225636B (it) 1990-11-22
IT8883689A0 (it) 1988-12-15
EP0375632A3 (de) 1993-04-21
DE68927852D1 (de) 1997-04-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee