DE69014018T2 - Halbleiteranordnung-Wannenoberfläche mit einer gleichmässigen Dotierung und Verfahren zur Herstellung. - Google Patents

Halbleiteranordnung-Wannenoberfläche mit einer gleichmässigen Dotierung und Verfahren zur Herstellung.

Info

Publication number
DE69014018T2
DE69014018T2 DE69014018T DE69014018T DE69014018T2 DE 69014018 T2 DE69014018 T2 DE 69014018T2 DE 69014018 T DE69014018 T DE 69014018T DE 69014018 T DE69014018 T DE 69014018T DE 69014018 T2 DE69014018 T2 DE 69014018T2
Authority
DE
Germany
Prior art keywords
manufacture
well surface
uniform doping
semiconductor array
array well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69014018T
Other languages
English (en)
Other versions
DE69014018D1 (de
Inventor
Munehiro Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69014018D1 publication Critical patent/DE69014018D1/de
Publication of DE69014018T2 publication Critical patent/DE69014018T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69014018T 1989-08-08 1990-08-07 Halbleiteranordnung-Wannenoberfläche mit einer gleichmässigen Dotierung und Verfahren zur Herstellung. Expired - Fee Related DE69014018T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1203771A JP2504573B2 (ja) 1989-08-08 1989-08-08 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
DE69014018D1 DE69014018D1 (de) 1994-12-15
DE69014018T2 true DE69014018T2 (de) 1995-04-20

Family

ID=16479537

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69014018T Expired - Fee Related DE69014018T2 (de) 1989-08-08 1990-08-07 Halbleiteranordnung-Wannenoberfläche mit einer gleichmässigen Dotierung und Verfahren zur Herstellung.

Country Status (5)

Country Link
US (1) US5110750A (de)
EP (1) EP0414040B1 (de)
JP (1) JP2504573B2 (de)
KR (1) KR930011173B1 (de)
DE (1) DE69014018T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512495A (en) * 1994-04-08 1996-04-30 Texas Instruments Incorporated Method of manufacturing extended drain resurf lateral DMOS devices
KR100260559B1 (ko) * 1997-12-29 2000-07-01 윤종용 비휘발성 메모리 장치의 웰 구조 및 그 제조 방법
US6051458A (en) * 1998-05-04 2000-04-18 Taiwan Semiconductor Manufacturing Company Drain and source engineering for ESD-protection transistors
US6995426B2 (en) * 2001-12-27 2006-02-07 Kabushiki Kaisha Toshiba Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type
JP2003258120A (ja) * 2002-03-07 2003-09-12 Seiko Epson Corp 半導体装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3719535A (en) * 1970-12-21 1973-03-06 Motorola Inc Hyperfine geometry devices and method for their fabrication
JPS55125660A (en) * 1979-03-22 1980-09-27 Toshiba Corp Production of semiconductor device
JPS5817655A (ja) * 1981-07-24 1983-02-01 Hitachi Ltd 半導体装置の製造方法
JPS60123055A (ja) * 1983-12-07 1985-07-01 Fujitsu Ltd 半導体装置及びその製造方法
JPS6184016A (ja) * 1984-10-02 1986-04-28 Nec Corp 半導体装置の製造方法
JPS61171165A (ja) * 1985-01-25 1986-08-01 Nissan Motor Co Ltd Ｍｏｓトランジスタ
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
EP0304541A1 (de) * 1987-08-18 1989-03-01 Deutsche ITT Industries GmbH Verfahren zum Herstellen implantierter Wannen und Inseln von integrierten CMOS-Schaltungen
JPH02105453A (ja) * 1988-10-13 1990-04-18 Nec Corp 半導体集積回路の製造方法
JPH02237159A (ja) * 1989-03-10 1990-09-19 Toshiba Corp 半導体装置

Also Published As

Publication number Publication date
US5110750A (en) 1992-05-05
JP2504573B2 (ja) 1996-06-05
EP0414040B1 (de) 1994-11-09
KR910005391A (ko) 1991-03-30
DE69014018D1 (de) 1994-12-15
KR930011173B1 (ko) 1993-11-24
JPH0369160A (ja) 1991-03-25
EP0414040A1 (de) 1991-02-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee