KR910005391A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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Publication number
KR910005391A
KR910005391A KR1019900012146A KR900012146A KR910005391A KR 910005391 A KR910005391 A KR 910005391A KR 1019900012146 A KR1019900012146 A KR 1019900012146A KR 900012146 A KR900012146 A KR 900012146A KR 910005391 A KR910005391 A KR 910005391A
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KR
South Korea
Prior art keywords
conductive
diffusion region
semiconductor device
surface concentration
manufacturing
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KR1019900012146A
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English (en)
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KR930011173B1 (ko
Inventor
무네히로 요시다
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910005391A publication Critical patent/KR910005391A/ko
Application granted granted Critical
Publication of KR930011173B1 publication Critical patent/KR930011173B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 관한 반도체장치를 도시한 단면도.
제2도는 본 발명의 제1실시예에 관한 반도체장치의 표면방향의 농도프로파일을 도시한 그래프.

Claims (4)

  1. 제1도전형 반도체기판(1,10)과, 이 반도체기판(1,10) 표면에 형성된 제2도전형 제1확산영역(2,11), 이 제1확산영역(2,11)의 중심부에 있어서의 표면농도보다도 낮은 표면 농도를 갖춘 주변부에 형성된 제2도전형 제2확산영역(3,13)을 구비한 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 상기 제1확산영역(2,11)의 중심부의 표면농도는 상기 제1확산영역(2,11)의 주변부의 표면농도와 상기 제2확산영역(3,13)의 표면농도의 합으로 실질상 같은 것을 특징으로 하는 반도체장치.
  3. 제1도전형 반도체기판(1,10) 표면에 제2도전형 불순물을 확산하고, 제1확산영역(2,11)을 형성하는 공정과, 상기 제1확산영역(2,11)의 중심부에 있어서의 표면농도보다도 낮은 표면농도를 갖춘 주변부에 제2도전형 불순물을 확산하는 공정을 구비한 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제3항에 있어서, 상기 제1확산영역(2,11)의 표면농도는 중심부와 주변부에서 실질상 같게 되는 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900012146A 1989-08-08 1990-08-08 반도체장치 및 그 제조방법 KR930011173B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1203771A JP2504573B2 (ja) 1989-08-08 1989-08-08 半導体装置及びその製造方法
JP01-203771 1989-08-08
JP1-203771 1989-08-08

Publications (2)

Publication Number Publication Date
KR910005391A true KR910005391A (ko) 1991-03-30
KR930011173B1 KR930011173B1 (ko) 1993-11-24

Family

ID=16479537

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900012146A KR930011173B1 (ko) 1989-08-08 1990-08-08 반도체장치 및 그 제조방법

Country Status (5)

Country Link
US (1) US5110750A (ko)
EP (1) EP0414040B1 (ko)
JP (1) JP2504573B2 (ko)
KR (1) KR930011173B1 (ko)
DE (1) DE69014018T2 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512495A (en) * 1994-04-08 1996-04-30 Texas Instruments Incorporated Method of manufacturing extended drain resurf lateral DMOS devices
KR100260559B1 (ko) * 1997-12-29 2000-07-01 윤종용 비휘발성 메모리 장치의 웰 구조 및 그 제조 방법
US6051458A (en) * 1998-05-04 2000-04-18 Taiwan Semiconductor Manufacturing Company Drain and source engineering for ESD-protection transistors
US6995426B2 (en) * 2001-12-27 2006-02-07 Kabushiki Kaisha Toshiba Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type
JP2003258120A (ja) * 2002-03-07 2003-09-12 Seiko Epson Corp 半導体装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3719535A (en) * 1970-12-21 1973-03-06 Motorola Inc Hyperfine geometry devices and method for their fabrication
JPS55125660A (en) * 1979-03-22 1980-09-27 Toshiba Corp Production of semiconductor device
JPS5817655A (ja) * 1981-07-24 1983-02-01 Hitachi Ltd 半導体装置の製造方法
JPS60123055A (ja) * 1983-12-07 1985-07-01 Fujitsu Ltd 半導体装置及びその製造方法
JPS6184016A (ja) * 1984-10-02 1986-04-28 Nec Corp 半導体装置の製造方法
JPS61171165A (ja) * 1985-01-25 1986-08-01 Nissan Motor Co Ltd Ｍｏｓトランジスタ
US4728619A (en) * 1987-06-19 1988-03-01 Motorola, Inc. Field implant process for CMOS using germanium
EP0304541A1 (de) * 1987-08-18 1989-03-01 Deutsche ITT Industries GmbH Verfahren zum Herstellen implantierter Wannen und Inseln von integrierten CMOS-Schaltungen
JPH02105453A (ja) * 1988-10-13 1990-04-18 Nec Corp 半導体集積回路の製造方法
JPH02237159A (ja) * 1989-03-10 1990-09-19 Toshiba Corp 半導体装置

Also Published As

Publication number Publication date
US5110750A (en) 1992-05-05
JPH0369160A (ja) 1991-03-25
DE69014018D1 (de) 1994-12-15
DE69014018T2 (de) 1995-04-20
EP0414040A1 (en) 1991-02-27
KR930011173B1 (ko) 1993-11-24
JP2504573B2 (ja) 1996-06-05
EP0414040B1 (en) 1994-11-09

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