KR900002408A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR900002408A
KR900002408A KR1019890010112A KR890010112A KR900002408A KR 900002408 A KR900002408 A KR 900002408A KR 1019890010112 A KR1019890010112 A KR 1019890010112A KR 890010112 A KR890010112 A KR 890010112A KR 900002408 A KR900002408 A KR 900002408A
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KR
South Korea
Prior art keywords
diffusion layer
type diffusion
manufacturing
semiconductor device
type
Prior art date
Application number
KR1019890010112A
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English (en)
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KR920009372B1 (ko
Inventor
다다시 마츠노
히데키 시바타
가즈히코 하시모토
히사요 사사키
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR900002408A publication Critical patent/KR900002408A/ko
Application granted granted Critical
Publication of KR920009372B1 publication Critical patent/KR920009372B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명의 실시예에 따른 반도체장치의 제조방법을 공정순으로 나타낸 단면도.

Claims (2)

  1. 제1도전형의 반도체기판(11) 내에 N형 확산층(21)과 P형 확산층(22)이 형성되어 있는 반도체장치의 제조방법에 있어서, 상기 N형 확산층(21) 및 P형 확산층(22)중의 어느 한쪽 확산층에 대한 접속구멍 형성공정이 다른 쪽의 확산층에 대한 접속구멍 형성공정보다 먼저 실행하도록 된 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 N형 확산층(21)에 대한 접속구멍을 먼저 형성시킨후라던지 상기 P형 확산층(22)에 대한 접속구멍을 먼저 형성시킨후 해당 N형 확산층(21)이나 P형 확산층(22)에 그 해당확산층과 동일한 전도형의 불순물을 도핑시킨 다음 열처리공정을 하도록 된 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890010112A 1988-07-15 1989-07-15 반도체장치의 제조방법 KR920009372B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP88-176723 1988-07-15
JP63176723A JP2645088B2 (ja) 1988-07-15 1988-07-15 半導体装置の製造方法
JP63-176723 1988-07-15

Publications (2)

Publication Number Publication Date
KR900002408A true KR900002408A (ko) 1990-02-28
KR920009372B1 KR920009372B1 (ko) 1992-10-15

Family

ID=16018653

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890010112A KR920009372B1 (ko) 1988-07-15 1989-07-15 반도체장치의 제조방법

Country Status (3)

Country Link
US (1) US5106782A (ko)
JP (1) JP2645088B2 (ko)
KR (1) KR920009372B1 (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5514616A (en) * 1991-08-26 1996-05-07 Lsi Logic Corporation Depositing and densifying glass to planarize layers in semi-conductor devices based on CMOS structures
US5646057A (en) * 1994-07-25 1997-07-08 Taiwan Semiconductor Manufacturing Company Method for a MOS device manufacturing
US5637525A (en) * 1995-10-20 1997-06-10 Micron Technology, Inc. Method of forming a CMOS circuitry
US5783470A (en) * 1995-12-14 1998-07-21 Lsi Logic Corporation Method of making CMOS dynamic random-access memory structures and the like
DE19628459A1 (de) * 1996-07-15 1998-01-29 Siemens Ag Halbleiterbauelement mit niedrigem Kontaktwiderstand zu hochdotierten Gebieten
JP3384714B2 (ja) 1997-07-16 2003-03-10 富士通株式会社 半導体装置およびその製造方法
JP2005248250A (ja) * 2004-03-04 2005-09-15 Teijin Ltd カスケード式に接続された選択的ポンプ群を備える化学気相蒸着装置と、カスケード式に接続された選択的ポンプ群のモニター装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6028397B2 (ja) * 1978-10-26 1985-07-04 株式会社東芝 半導体装置の製造方法
JPS56129364A (en) * 1980-03-14 1981-10-09 Nec Corp Complementary field effect transistor
JPS56134757A (en) * 1980-03-26 1981-10-21 Nec Corp Complementary type mos semiconductor device and its manufacture
JPS5744022A (en) * 1980-08-28 1982-03-12 Jiyouban Kiso:Kk Hydraulic lifting, dead weight drop system pile driving device
US4512073A (en) * 1984-02-23 1985-04-23 Rca Corporation Method of forming self-aligned contact openings
US4535532A (en) * 1984-04-09 1985-08-20 At&T Bell Laboratories Integrated circuit contact technique
US4549914A (en) * 1984-04-09 1985-10-29 At&T Bell Laboratories Integrated circuit contact technique
JPS61116870A (ja) * 1984-11-13 1986-06-04 Seiko Epson Corp 半導体装置の製造方法
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
JPS63128626A (ja) * 1986-11-18 1988-06-01 Nec Corp 半導体集積回路装置のコンタクト形成方法

Also Published As

Publication number Publication date
KR920009372B1 (ko) 1992-10-15
JP2645088B2 (ja) 1997-08-25
US5106782A (en) 1992-04-21
JPH0227716A (ja) 1990-01-30

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