KR920003532A - 마스터 슬라이스 방식에 있어서의 반도체집적회로의 제조방법 - Google Patents

마스터 슬라이스 방식에 있어서의 반도체집적회로의 제조방법 Download PDF

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Publication number
KR920003532A
KR920003532A KR1019910012006A KR910012006A KR920003532A KR 920003532 A KR920003532 A KR 920003532A KR 1019910012006 A KR1019910012006 A KR 1019910012006A KR 910012006 A KR910012006 A KR 910012006A KR 920003532 A KR920003532 A KR 920003532A
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South Korea
Prior art keywords
integrated circuit
master slice
semiconductor integrated
manufacturing
layer
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KR1019910012006A
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English (en)
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KR950001759B1 (ko
Inventor
마사토 나가미츠
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR920003532A publication Critical patent/KR920003532A/ko
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Publication of KR950001759B1 publication Critical patent/KR950001759B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/909—Macrocell arrays, e.g. gate arrays with variable size or configuration of cells

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.

Description

마스터 슬라이스 방식에 있어서의 반도체집적회로의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 제1실시예에 따른 구성을 나타낸 패턴평면도.
제2도는 본 발명의 제2실시예에 따른 구성을 나타낸 패턴평면도.
제3도는 본 발명의 제3실시예에 따른 구성을 나타낸 패턴평면도.
제4도는 제3도에 있어서의 일부 확대평면도.
제5도는 본 발명의 제4실시예에 따른 구성을 나타낸 패턴평면도.
제6도는 본 발명의 종래기술을 비교하여 나타낸 평가도이다.
* 도면의 주요부분에 대한 부호의 설명
11 : P형 확산영역 12 : N형 확산영역
13, 14 : 게이트 15, 16 : 금석배선
17, 18 : 게이트전극 19, 20 : 기판전극

Claims (2)

  1. M층 금속배선(M＞2)을 갖춘 마스터 슬라이스 방식의 반도체집적회로에 있어서, 상기 M층 금속배선중 최하층으로부터 m층(M-m)까지를 공통 사용하는 웨이퍼에 구비시켜서 이를 마스터 슬라이스로 하며, 나머지 M-m층의 금속배선을 필요한 논리기능을 얻기 위한 퍼스널라이즈에 사용하는 것을 특징으로 하는 마스터 슬라이스 방식에 있어서의 반도체집적회로의 제조방법.
  2. 제1항에 있어서, 상기 M층 금속배선중 최하층을 전원배선(34,35)으로 사용하는 것을 특징으로 하는 마스터 슬라이스 방식에 있어서의 반도체직접회로의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019910012006A 1990-07-16 1991-07-15 마스터 슬라이스 방식에 있어서의 반도체집적회로의 제조방법 KR950001759B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2-187751 1990-07-16
JP2187751A JP2953755B2 (ja) 1990-07-16 1990-07-16 マスタスライス方式の半導体装置
JP90-187751 1990-07-16

Publications (2)

Publication Number Publication Date
KR920003532A true KR920003532A (ko) 1992-02-29
KR950001759B1 KR950001759B1 (ko) 1995-02-28

Family

ID=16211566

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910012006A KR950001759B1 (ko) 1990-07-16 1991-07-15 마스터 슬라이스 방식에 있어서의 반도체집적회로의 제조방법

Country Status (3)

Country Link
US (1) US5171701A (ko)
JP (1) JP2953755B2 (ko)
KR (1) KR950001759B1 (ko)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5796129A (en) * 1993-08-03 1998-08-18 Seiko Epson Corp. Master slice type integrated circuit system having block areas optimized based on function
US5737580A (en) * 1995-04-28 1998-04-07 International Business Machines Corporation Wiring design tool improvement for avoiding electromigration by determining optimal wire widths
JP3406809B2 (ja) * 1997-08-27 2003-05-19 沖電気工業株式会社 自動配置配線装置のためのライブラリ
JP4387654B2 (ja) * 2002-10-10 2009-12-16 パナソニック株式会社 半導体装置およびその製造方法
JP2005268245A (ja) * 2004-03-16 2005-09-29 Nec Electronics Corp 半導体装置の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5843905B2 (ja) * 1979-07-31 1983-09-29 富士通株式会社 半導体集積回路の製造方法
JPS5690548A (en) * 1979-11-20 1981-07-22 Fujitsu Ltd Manufacture of semiconductor device by master slice system
US4742383A (en) * 1983-01-12 1988-05-03 International Business Machines Corporation Multi-function FET masterslice cell
JPS6035532A (ja) * 1983-07-29 1985-02-23 Fujitsu Ltd マスタスライス集積回路装置
US4633571A (en) * 1984-04-16 1987-01-06 At&T Bell Laboratories Method of manufacturing a CMOS cell array with transistor isolation
DE3585756D1 (de) * 1984-07-02 1992-05-07 Fujitsu Ltd Halbleiterschaltungsanordnung in hauptscheibentechnik.
JPH0728013B2 (ja) * 1988-06-13 1995-03-29 松下電子工業株式会社 マスタースライス方式半導体集積回路装置の製造方法
JPH01144667A (ja) * 1987-11-30 1989-06-06 Toshiba Corp 基板電位検出回路
JPH01298736A (ja) * 1988-05-27 1989-12-01 Hitachi Ltd 半導体装置
JPH02111067A (ja) * 1988-10-20 1990-04-24 Fujitsu Ltd マスタスライス

Also Published As

Publication number Publication date
JP2953755B2 (ja) 1999-09-27
US5171701A (en) 1992-12-15
KR950001759B1 (ko) 1995-02-28
JPH0473966A (ja) 1992-03-09

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