DE69704888D1 - Steuerschaltung für den Datenausgang für eine Halbleiterspeicheranordnung mit einer Pipelinestruktur - Google Patents

Steuerschaltung für den Datenausgang für eine Halbleiterspeicheranordnung mit einer Pipelinestruktur

Info

Publication number
DE69704888D1
DE69704888D1 DE69704888T DE69704888T DE69704888D1 DE 69704888 D1 DE69704888 D1 DE 69704888D1 DE 69704888 T DE69704888 T DE 69704888T DE 69704888 T DE69704888 T DE 69704888T DE 69704888 D1 DE69704888 D1 DE 69704888D1
Authority
DE
Germany
Prior art keywords
signals
signal
data
memory cells
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69704888T
Other languages
English (en)
Other versions
DE69704888T2 (de
Inventor
Yasuji Koshikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69704888D1 publication Critical patent/DE69704888D1/de
Application granted granted Critical
Publication of DE69704888T2 publication Critical patent/DE69704888T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/88—Monitoring involving counting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
DE69704888T 1996-01-23 1997-01-20 Steuerschaltung für den Datenausgang für eine Halbleiterspeicheranordnung mit einer Pipelinestruktur Expired - Lifetime DE69704888T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8009121A JP2833563B2 (ja) 1996-01-23 1996-01-23 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69704888D1 true DE69704888D1 (de) 2001-06-28
DE69704888T2 DE69704888T2 (de) 2002-03-28

Family

ID=11711813

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69704888T Expired - Lifetime DE69704888T2 (de) 1996-01-23 1997-01-20 Steuerschaltung für den Datenausgang für eine Halbleiterspeicheranordnung mit einer Pipelinestruktur

Country Status (5)

Country Link
US (1) US5708614A (de)
EP (1) EP0786780B1 (de)
JP (1) JP2833563B2 (de)
KR (1) KR100269504B1 (de)
DE (1) DE69704888T2 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0845788B1 (de) * 1996-11-27 2003-09-10 Texas Instruments Incorporated Speicherfeldprüfschaltung mit Fehlermeldung
US5933369A (en) * 1997-02-28 1999-08-03 Xilinx, Inc. RAM with synchronous write port using dynamic latches
JP4221764B2 (ja) * 1997-04-25 2009-02-12 沖電気工業株式会社 半導体記憶装置
KR100264076B1 (ko) * 1997-06-20 2000-08-16 김영환 데이타 출력 드라이버 전류를 증가시킨 디램
KR100265760B1 (ko) * 1997-12-03 2000-09-15 윤종용 직접엑세스모드테스트제어회로를구비하는고속반도체메모리장치및테스트방법
KR100238256B1 (ko) * 1997-12-03 2000-01-15 윤종용 직접 억세스 모드 테스트를 사용하는 메모리 장치 및 테스트방법
JP2000003589A (ja) * 1998-06-12 2000-01-07 Mitsubishi Electric Corp 同期型半導体記憶装置
US6181616B1 (en) 1998-09-03 2001-01-30 Micron Technology, Inc. Circuits and systems for realigning data output by semiconductor testers to packet-based devices under test
US6374376B1 (en) 1998-09-03 2002-04-16 Micron Technology, Inc. Circuit, system and method for arranging data output by semiconductor testers to packet-based devices under test
KR100365562B1 (ko) * 1998-12-30 2003-02-20 주식회사 하이닉스반도체 반도체 기억소자의 테스트회로
JP3484388B2 (ja) * 2000-02-08 2004-01-06 日本電気株式会社 半導体記憶装置
JP2001297600A (ja) 2000-04-11 2001-10-26 Mitsubishi Electric Corp 半導体集積回路およびそのテスト方法
JP3645791B2 (ja) * 2000-05-29 2005-05-11 エルピーダメモリ株式会社 同期型半導体記憶装置
JP4430801B2 (ja) * 2000-08-03 2010-03-10 株式会社アドバンテスト 半導体メモリ試験装置
KR100416619B1 (ko) * 2002-04-06 2004-02-05 삼성전자주식회사 동기식 반도체 장치의 데이터 출력 회로 및 그 방법
JP4540433B2 (ja) * 2004-09-06 2010-09-08 ルネサスエレクトロニクス株式会社 入出力縮退回路
KR100850270B1 (ko) * 2007-02-08 2008-08-04 삼성전자주식회사 페일비트 저장부를 갖는 반도체 메모리 장치
JP2010198715A (ja) * 2009-02-27 2010-09-09 Elpida Memory Inc 半導体記憶装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61148692A (ja) 1984-12-24 1986-07-07 Nippon Telegr & Teleph Corp <Ntt> 記憶装置
JPH02146199A (ja) * 1988-11-28 1990-06-05 Mitsubishi Electric Corp 半導体記憶装置のテスト回路
JPH03222200A (ja) 1990-01-26 1991-10-01 Mitsubishi Electric Corp ラインモードテスト機能付半導体記憶装置
JPH0447590A (ja) 1990-06-15 1992-02-17 Sharp Corp メモリ内蔵型集積回路装置
KR960009033B1 (en) * 1991-07-17 1996-07-10 Toshiba Kk Semiconductor memory
JP2830594B2 (ja) * 1992-03-26 1998-12-02 日本電気株式会社 半導体メモリ装置
JP2792331B2 (ja) 1992-05-14 1998-09-03 日本電気株式会社 半導体記憶装置
JP2765376B2 (ja) * 1992-07-02 1998-06-11 日本電気株式会社 半導体メモリ
JPH0676598A (ja) * 1992-08-28 1994-03-18 Mitsubishi Electric Corp 半導体記憶装置

Also Published As

Publication number Publication date
EP0786780B1 (de) 2001-05-23
US5708614A (en) 1998-01-13
JPH09198895A (ja) 1997-07-31
KR970060247A (ko) 1997-08-12
JP2833563B2 (ja) 1998-12-09
EP0786780A1 (de) 1997-07-30
KR100269504B1 (ko) 2000-10-16
DE69704888T2 (de) 2002-03-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

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