DE60103154D1 - Automatisches gerät für testbarkeitsanalyse - Google Patents

Automatisches gerät für testbarkeitsanalyse

Info

Publication number
DE60103154D1
DE60103154D1 DE60103154T DE60103154T DE60103154D1 DE 60103154 D1 DE60103154 D1 DE 60103154D1 DE 60103154 T DE60103154 T DE 60103154T DE 60103154 T DE60103154 T DE 60103154T DE 60103154 D1 DE60103154 D1 DE 60103154D1
Authority
DE
Germany
Prior art keywords
binary decision
signal
state
given signal
automatic device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60103154T
Other languages
English (en)
Other versions
DE60103154T2 (de
Inventor
Florence Akli
Alain Debreil
Christian Niquet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SAS
Original Assignee
Bull SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SAS filed Critical Bull SAS
Publication of DE60103154D1 publication Critical patent/DE60103154D1/de
Application granted granted Critical
Publication of DE60103154T2 publication Critical patent/DE60103154T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318371—Methodologies therefor, e.g. algorithms, procedures

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
  • Logic Circuits (AREA)
  • Automatic Analysis And Handling Materials Therefor (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE60103154T 2000-06-08 2001-06-07 Automatisches gerät für testbarkeitsanalyse Expired - Lifetime DE60103154T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0007354 2000-06-08
FR0007354A FR2810126B1 (fr) 2000-06-08 2000-06-08 Outil automatique d'analyse de testabilite
PCT/FR2001/001764 WO2001094960A1 (fr) 2000-06-08 2001-06-07 Outil automatique d'analyse de testabilite

Publications (2)

Publication Number Publication Date
DE60103154D1 true DE60103154D1 (de) 2004-06-09
DE60103154T2 DE60103154T2 (de) 2005-06-09

Family

ID=8851099

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60103154T Expired - Lifetime DE60103154T2 (de) 2000-06-08 2001-06-07 Automatisches gerät für testbarkeitsanalyse

Country Status (6)

Country Link
US (1) US20020156540A1 (de)
EP (1) EP1292839B1 (de)
AT (1) ATE266209T1 (de)
DE (1) DE60103154T2 (de)
FR (1) FR2810126B1 (de)
WO (1) WO2001094960A1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7551572B2 (en) * 2005-10-21 2009-06-23 Isilon Systems, Inc. Systems and methods for providing variable protection
US7739635B2 (en) * 2007-05-10 2010-06-15 International Business Machines Corporation Conjunctive BDD building and variable quantification using case-splitting
CN104515950B (zh) * 2015-01-12 2018-05-22 华南师范大学 一种集成电路的内建自测试方法及应用

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5481717A (en) * 1993-04-12 1996-01-02 Kabushiki Kaisha Toshiba Logic program comparison method for verifying a computer program in relation to a system specification
US5572535A (en) * 1994-07-05 1996-11-05 Motorola Inc. Method and data processing system for verifying the correct operation of a tri-state multiplexer in a circuit design
US5752000A (en) * 1994-08-02 1998-05-12 Cadence Design Systems, Inc. System and method for simulating discrete functions using ordered decision arrays
FR2810127B1 (fr) * 2000-06-08 2002-08-16 Bull Sa Procede pour mettre en evidence la dependance d'un signal en fonction d'un autre signal

Also Published As

Publication number Publication date
EP1292839A1 (de) 2003-03-19
FR2810126A1 (fr) 2001-12-14
DE60103154T2 (de) 2005-06-09
WO2001094960A1 (fr) 2001-12-13
EP1292839B1 (de) 2004-05-06
FR2810126B1 (fr) 2004-03-12
US20020156540A1 (en) 2002-10-24
ATE266209T1 (de) 2004-05-15

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: BULL S.A., LES CLAYES SOUS BOIS, FR

8364 No opposition during term of opposition