DE602006013339D1 - Ic-testverfahren und vorrichtung - Google Patents

Ic-testverfahren und vorrichtung

Info

Publication number
DE602006013339D1
DE602006013339D1 DE602006013339T DE602006013339T DE602006013339D1 DE 602006013339 D1 DE602006013339 D1 DE 602006013339D1 DE 602006013339 T DE602006013339 T DE 602006013339T DE 602006013339 T DE602006013339 T DE 602006013339T DE 602006013339 D1 DE602006013339 D1 DE 602006013339D1
Authority
DE
Germany
Prior art keywords
shift register
circuit
serial
storage element
testing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006013339T
Other languages
English (en)
Inventor
Tom Waayers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602006013339D1 publication Critical patent/DE602006013339D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
DE602006013339T 2005-10-24 2006-10-12 Ic-testverfahren und vorrichtung Active DE602006013339D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP05109892 2005-10-24
PCT/IB2006/053754 WO2007049171A1 (en) 2005-10-24 2006-10-12 Ic testing methods and apparatus

Publications (1)

Publication Number Publication Date
DE602006013339D1 true DE602006013339D1 (de) 2010-05-12

Family

ID=37814489

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006013339T Active DE602006013339D1 (de) 2005-10-24 2006-10-12 Ic-testverfahren und vorrichtung

Country Status (8)

Country Link
US (1) US7870449B2 (de)
EP (1) EP1943531B1 (de)
JP (1) JP5171632B2 (de)
CN (1) CN101297208B (de)
AT (1) ATE462980T1 (de)
DE (1) DE602006013339D1 (de)
TW (1) TW200732686A (de)
WO (1) WO2007049171A1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7941717B2 (en) 2005-10-24 2011-05-10 Nxp B.V. IC testing methods and apparatus
EP1943533B1 (de) 2005-10-24 2010-06-23 Nxp B.V. Ic-testverfahren und vorrichtung
US7958479B2 (en) * 2007-12-04 2011-06-07 Alcatel-Lucent Usa Inc. Method and apparatus for describing and testing a system-on-chip
US7962885B2 (en) 2007-12-04 2011-06-14 Alcatel-Lucent Usa Inc. Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testing
US7949915B2 (en) 2007-12-04 2011-05-24 Alcatel-Lucent Usa Inc. Method and apparatus for describing parallel access to a system-on-chip
US7958417B2 (en) 2008-01-30 2011-06-07 Alcatel-Lucent Usa Inc. Apparatus and method for isolating portions of a scan path of a system-on-chip
US7954022B2 (en) 2008-01-30 2011-05-31 Alcatel-Lucent Usa Inc. Apparatus and method for controlling dynamic modification of a scan path
WO2010011208A1 (en) * 2008-07-25 2010-01-28 Thomson Licensing Method and apparatus for a reconfigurable at-speed test clock generator
US8296694B1 (en) * 2009-12-30 2012-10-23 Cadence Design Systems, Inc. System and method for automated synthesis of circuit wrappers
US9043665B2 (en) * 2011-03-09 2015-05-26 Intel Corporation Functional fabric based test wrapper for circuit testing of IP blocks
CN102305909B (zh) * 2011-09-09 2013-12-04 西安华芯半导体有限公司 分布式测试节点链及其多链系统
US9164943B2 (en) 2012-01-18 2015-10-20 Intel Corporation Self correction logic for serial-to-parallel converters
US8914693B2 (en) * 2012-02-15 2014-12-16 International Business Machines Corporation Apparatus for JTAG-driven remote scanning
CN102749574B (zh) * 2012-07-18 2014-11-12 中国科学院微电子研究所 扫描测试方法及电路
US9121892B2 (en) * 2012-08-13 2015-09-01 Analog Devices Global Semiconductor circuit and methodology for in-system scan testing
CN103279405A (zh) * 2013-05-30 2013-09-04 南京航空航天大学 适用于片上网络嵌入式ip核的测试壳
KR102225314B1 (ko) * 2014-11-17 2021-03-10 에스케이하이닉스 주식회사 반도체 장치 및 동작 방법
US20160349320A1 (en) * 2015-05-26 2016-12-01 Qualcomm Incorporated Remote bus wrapper for testing remote cores using automatic test pattern generation and other techniques
US10386411B2 (en) 2017-08-23 2019-08-20 Stmicroelectronics International N.V. Sequential test access port selection in a JTAG interface
US10495690B2 (en) 2017-08-28 2019-12-03 Stmicroelectronics International N.V. Combinatorial serial and parallel test access port selection in a JTAG interface
CN109192240B (zh) * 2018-08-28 2023-12-05 长鑫存储技术有限公司 边界测试电路、存储器及边界测试方法
US11047909B2 (en) * 2018-10-30 2021-06-29 Maxlinear, Inc. Inter-domain power element testing using scan
US11720719B2 (en) * 2019-10-01 2023-08-08 Micron Technology, Inc. Apparatuses and methods for signal encryption in high bandwidth memory
US11320485B1 (en) * 2020-12-31 2022-05-03 Nxp Usa, Inc. Scan wrapper architecture for system-on-chip
US11675589B2 (en) * 2021-09-01 2023-06-13 Micron Technology, Inc. Serial interfaces with shadow registers, and associated systems, devices, and methods
WO2023192671A1 (en) * 2022-04-01 2023-10-05 Google Llc Custom wrapper cell for hardware testing

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6304987B1 (en) * 1995-06-07 2001-10-16 Texas Instruments Incorporated Integrated test circuit
JPH11264854A (ja) * 1998-03-18 1999-09-28 Oki Electric Ind Co Ltd 半導体集積回路および半導体集積回路の試験方法
US6560734B1 (en) * 1998-06-19 2003-05-06 Texas Instruments Incorporated IC with addressable test port
JP2000029736A (ja) * 1998-07-13 2000-01-28 Oki Electric Ind Co Ltd 半導体集積回路
US6877122B2 (en) * 2001-12-21 2005-04-05 Texas Instruments Incorporated Link instruction register providing test control signals to core wrappers
US6925583B1 (en) * 2002-01-09 2005-08-02 Xilinx, Inc. Structure and method for writing from a JTAG device with microcontroller to a non-JTAG device
JP4274806B2 (ja) * 2003-01-28 2009-06-10 株式会社リコー 半導体集積回路およびスキャンテスト法
ATE347112T1 (de) * 2003-02-10 2006-12-15 Koninkl Philips Electronics Nv Testen von integrierten schaltungen
JP2004280926A (ja) * 2003-03-14 2004-10-07 Renesas Technology Corp 半導体記憶装置
DE602005008552D1 (de) * 2004-01-19 2008-09-11 Nxp Bv Testarchitektur und -verfahren
US7725784B2 (en) * 2004-02-17 2010-05-25 Institut National Polytechnique De Grenoble Integrated circuit chip with communication means enabling remote control of testing means of IP cores of the integrated circuit
TWI263058B (en) * 2004-12-29 2006-10-01 Ind Tech Res Inst Wrapper testing circuits and method thereof for system-on-a-chip

Also Published As

Publication number Publication date
JP2009512872A (ja) 2009-03-26
CN101297208A (zh) 2008-10-29
CN101297208B (zh) 2012-05-30
EP1943531B1 (de) 2010-03-31
JP5171632B2 (ja) 2013-03-27
EP1943531A1 (de) 2008-07-16
ATE462980T1 (de) 2010-04-15
WO2007049171A1 (en) 2007-05-03
US20080290878A1 (en) 2008-11-27
TW200732686A (en) 2007-09-01
US7870449B2 (en) 2011-01-11

Similar Documents

Publication Publication Date Title
DE602006013339D1 (de) Ic-testverfahren und vorrichtung
TW200736901A (en) Method and device for monitoring operations of computer system
DE602005008552D1 (de) Testarchitektur und -verfahren
ATE456805T1 (de) Ic-testverfahren und vorrichtung
TW200708750A (en) Testable integrated circuit, system in package and test instruction set
DE602006015082D1 (de) Ic-testverfahren und vorrichtung
ATE521902T1 (de) Integrierte halbleiterschaltung und verfahren zur speicherung und wiederherstellung des inneren zustandes derselben
ATE531131T1 (de) Verfahren und vorrichtung zum verteilen mehrerer signaleingänge an mehrere integrierte schaltungen
EP2428808B1 (de) Integrierter schaltkreis mit erfassungskette und chiptestverfahren
WO2007080527A3 (en) Testable integrated circuit and ic test method
KR900005472A (ko) 검사 버퍼/레지스터
HK1148107A1 (en) An integrated circuit and method
ATE436029T1 (de) Analog-ic mit testanordnung und testverfahren für ein solches ic
TW200632347A (en) Integrated circuit and a method for testing a multi-tap integrated circuit
TW200601343A (en) Semiconductor memory device and method of testing semiconductor memory device
TW200629284A (en) Semiconductor memory device and method of testing the same
WO2003096034A3 (en) Tester system having multiple instruction memories
EP1394560A3 (de) Halbleiterchip-testsystem und entsprechender testverfahren
ATE293797T1 (de) Testzugriffs-portsteuerungsvorrichtung (tap) und verfahren zur beseitigung interner intermediärer abtastprüffehler
TW200601351A (en) Semiconductor memory device having test mode for data access time
DE60019255D1 (de) Verfahren und Vorrichtung zur Trimmung von elektronischen Schaltungen
TW200631025A (en) Method and system for timing measurement of embedded macro module
WO2008120362A1 (ja) 不良箇所特定装置、不良箇所特定方法および集積回路
TW200608030A (en) Testing method and testing circuit for a semiconductor device
KR880003248A (ko) 반도체 집적회로장치

Legal Events

Date Code Title Description
8364 No opposition during term of opposition