DE69432452T2 - Programmierte Referenz - Google Patents

Programmierte Referenz Download PDF

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Publication number
DE69432452T2
DE69432452T2 DE69432452T DE69432452T DE69432452T2 DE 69432452 T2 DE69432452 T2 DE 69432452T2 DE 69432452 T DE69432452 T DE 69432452T DE 69432452 T DE69432452 T DE 69432452T DE 69432452 T2 DE69432452 T2 DE 69432452T2
Authority
DE
Germany
Prior art keywords
cell
program
signal
array
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69432452T
Other languages
German (de)
English (en)
Other versions
DE69432452D1 (de
Inventor
Shane C. Hollmer
Lee E. Cleveland
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=22577486&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69432452(T2) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of DE69432452D1 publication Critical patent/DE69432452D1/de
Application granted granted Critical
Publication of DE69432452T2 publication Critical patent/DE69432452T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Read Only Memory (AREA)
DE69432452T 1993-12-01 1994-11-10 Programmierte Referenz Expired - Fee Related DE69432452T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/160,582 US5828601A (en) 1993-12-01 1993-12-01 Programmed reference
US160582 1993-12-01

Publications (2)

Publication Number Publication Date
DE69432452D1 DE69432452D1 (de) 2003-05-15
DE69432452T2 true DE69432452T2 (de) 2004-03-11

Family

ID=22577486

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69432452T Expired - Fee Related DE69432452T2 (de) 1993-12-01 1994-11-10 Programmierte Referenz

Country Status (6)

Country Link
US (1) US5828601A (enExample)
EP (1) EP0656628B1 (enExample)
JP (2) JP3813640B2 (enExample)
KR (1) KR100357444B1 (enExample)
DE (1) DE69432452T2 (enExample)
TW (1) TW302479B (enExample)

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US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
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FR2794277B1 (fr) * 1999-05-25 2001-08-10 St Microelectronics Sa Memoire morte a faible consommation
US6215702B1 (en) 2000-02-16 2001-04-10 Advanced Micro Devices, Inc. Method of maintaining constant erasing speeds for non-volatile memory cells
JP3776307B2 (ja) * 2000-04-26 2006-05-17 沖電気工業株式会社 不揮発性メモリアナログ電圧書き込み回路
US6928001B2 (en) 2000-12-07 2005-08-09 Saifun Semiconductors Ltd. Programming and erasing methods for a non-volatile memory cell
US6396741B1 (en) 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6490204B2 (en) * 2000-05-04 2002-12-03 Saifun Semiconductors Ltd. Programming and erasing methods for a reference cell of an NROM array
US6538922B1 (en) 2000-09-27 2003-03-25 Sandisk Corporation Writable tracking cells
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US6614692B2 (en) 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
US6538923B1 (en) * 2001-02-26 2003-03-25 Advanced Micro Devices, Inc. Staircase program verify for multi-level cell flash memory designs
US6466480B2 (en) * 2001-03-27 2002-10-15 Micron Technology, Inc. Method and apparatus for trimming non-volatile memory cells
IL148960A (en) * 2001-04-05 2005-09-25 Saifun Semiconductors Ltd Method for programming a reference cell
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
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US6643169B2 (en) * 2001-09-18 2003-11-04 Intel Corporation Variable level memory
US6678192B2 (en) 2001-11-02 2004-01-13 Sandisk Corporation Error management for writable tracking storage units
DE60134870D1 (de) * 2001-12-28 2008-08-28 St Microelectronics Srl Programmierverfahren für eine Multibitspeicherzelle
US6975536B2 (en) * 2002-01-31 2005-12-13 Saifun Semiconductors Ltd. Mass storage array and methods for operation thereof
US7190620B2 (en) 2002-01-31 2007-03-13 Saifun Semiconductors Ltd. Method for operating a memory device
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6826107B2 (en) 2002-08-01 2004-11-30 Saifun Semiconductors Ltd. High voltage insertion in flash memory cards
US6992932B2 (en) 2002-10-29 2006-01-31 Saifun Semiconductors Ltd Method circuit and system for read error detection in a non-volatile memory array
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US6963505B2 (en) * 2002-10-29 2005-11-08 Aifun Semiconductors Ltd. Method circuit and system for determining a reference voltage
US6967896B2 (en) 2003-01-30 2005-11-22 Saifun Semiconductors Ltd Address scramble
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7237074B2 (en) * 2003-06-13 2007-06-26 Sandisk Corporation Tracking cells for a memory system
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US6954393B2 (en) * 2003-09-16 2005-10-11 Saifun Semiconductors Ltd. Reading array cell with matched reference cell
US7301807B2 (en) 2003-10-23 2007-11-27 Sandisk Corporation Writable tracking cells
US7652930B2 (en) 2004-04-01 2010-01-26 Saifun Semiconductors Ltd. Method, circuit and system for erasing one or more non-volatile memory cells
US7755938B2 (en) * 2004-04-19 2010-07-13 Saifun Semiconductors Ltd. Method for reading a memory array with neighbor effect cancellation
US7366025B2 (en) 2004-06-10 2008-04-29 Saifun Semiconductors Ltd. Reduced power programming of non-volatile cells
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
ITMI20041927A1 (it) * 2004-10-12 2005-01-12 Atmel Corp Sistema e metodo pee evitare l'offset e ridurre il footprint di una memoria non volatile
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7257025B2 (en) * 2004-12-09 2007-08-14 Saifun Semiconductors Ltd Method for reading non-volatile memory cells
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
EP1831892A4 (en) * 2004-12-23 2009-06-10 Atmel Corp SYSTEM FOR IMPLEMENTING QUICK TEST DURING THE ADJUSTMENT OF FLASH REFERENCE CELLS
EP1686592A3 (en) 2005-01-19 2007-04-25 Saifun Semiconductors Ltd. Partial erase verify
US8053812B2 (en) * 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
US7184313B2 (en) 2005-06-17 2007-02-27 Saifun Semiconductors Ltd. Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
US7786512B2 (en) 2005-07-18 2010-08-31 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7221138B2 (en) * 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
JP2007164934A (ja) * 2005-12-16 2007-06-28 Fujitsu Ltd 不揮発性半導体記憶装置
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
KR100772389B1 (ko) * 2006-01-12 2007-11-01 삼성전자주식회사 메모리 인식 장치
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7638835B2 (en) * 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7388781B2 (en) 2006-03-06 2008-06-17 Sandisk Il Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US8848442B2 (en) 2006-03-06 2014-09-30 Sandisk Il Ltd. Multi-bit-per-cell flash memory device with non-bijective mapping
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
ITMI20062211A1 (it) * 2006-11-17 2008-05-18 St Microelectronics Srl Circuito e metodo per generare una tensione di riferimento in dispositivi di memoria a matrice di celle non volatili
US7590001B2 (en) 2007-12-18 2009-09-15 Saifun Semiconductors Ltd. Flash memory with optimized write sector spares
US7778098B2 (en) * 2007-12-31 2010-08-17 Cypress Semiconductor Corporation Dummy cell for memory circuits
US20090219776A1 (en) 2008-02-29 2009-09-03 Xian Liu Non-volatile memory device with plural reference cells, and method of setting the reference cells
KR101055568B1 (ko) 2009-06-17 2011-08-08 한양대학교 산학협력단 플래시 메모리 장치의 센싱 회로 및 플래시 메모리 장치의 센싱 방법
US9424946B2 (en) * 2013-02-08 2016-08-23 Seagate Technology Llc Non-volatile buffering to enable sloppy writes and fast write verification
KR102111510B1 (ko) * 2014-04-10 2020-05-19 에스케이하이닉스 주식회사 전자 장치
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US11823739B2 (en) * 2020-04-06 2023-11-21 Crossbar, Inc. Physically unclonable function (PUF) generation involving high side programming of bits
US11727986B2 (en) * 2020-04-06 2023-08-15 Crossbar, Inc. Physically unclonable function (PUF) generation involving programming of marginal bits
US12087397B1 (en) 2020-04-06 2024-09-10 Crossbar, Inc. Dynamic host allocation of physical unclonable feature operation for resistive switching memory
CN115273934A (zh) 2020-04-06 2022-11-01 昕原半导体(上海)有限公司 利用芯片上电阻存储器阵列的不可克隆特性的独特芯片标识符

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Also Published As

Publication number Publication date
JP3813640B2 (ja) 2006-08-23
EP0656628A2 (en) 1995-06-07
TW302479B (enExample) 1997-04-11
US5828601A (en) 1998-10-27
KR950020743A (ko) 1995-07-24
EP0656628A3 (en) 1995-08-09
DE69432452D1 (de) 2003-05-15
EP0656628B1 (en) 2003-04-09
JPH07192478A (ja) 1995-07-28
JP2006196184A (ja) 2006-07-27
KR100357444B1 (ko) 2003-01-24

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: SPANSION LLC (N.D.GES.D. STAATES DELAWARE), SU, US

8339 Ceased/non-payment of the annual fee