DE69411428T2 - Mit einem externen Taktsignal synchronisierte Halbleiterspeicheranordnung zum Ausgeben von Datenbits durch eine kleine Anzahl von Datenleitungen - Google Patents

Mit einem externen Taktsignal synchronisierte Halbleiterspeicheranordnung zum Ausgeben von Datenbits durch eine kleine Anzahl von Datenleitungen

Info

Publication number
DE69411428T2
DE69411428T2 DE69411428T DE69411428T DE69411428T2 DE 69411428 T2 DE69411428 T2 DE 69411428T2 DE 69411428 T DE69411428 T DE 69411428T DE 69411428 T DE69411428 T DE 69411428T DE 69411428 T2 DE69411428 T2 DE 69411428T2
Authority
DE
Germany
Prior art keywords
clock signal
memory device
semiconductor memory
small number
external clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69411428T
Other languages
English (en)
Other versions
DE69411428D1 (de
Inventor
Yasuhiro Takai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69411428D1 publication Critical patent/DE69411428D1/de
Application granted granted Critical
Publication of DE69411428T2 publication Critical patent/DE69411428T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
DE69411428T 1993-04-02 1994-03-30 Mit einem externen Taktsignal synchronisierte Halbleiterspeicheranordnung zum Ausgeben von Datenbits durch eine kleine Anzahl von Datenleitungen Expired - Lifetime DE69411428T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5077236A JPH06290582A (ja) 1993-04-02 1993-04-02 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69411428D1 DE69411428D1 (de) 1998-08-13
DE69411428T2 true DE69411428T2 (de) 1999-03-04

Family

ID=13628237

Family Applications (2)

Application Number Title Priority Date Filing Date
DE69430076T Expired - Lifetime DE69430076T2 (de) 1993-04-02 1994-03-30 Halbleiterspeicher und Zugriffverfahren für solchen Speicher
DE69411428T Expired - Lifetime DE69411428T2 (de) 1993-04-02 1994-03-30 Mit einem externen Taktsignal synchronisierte Halbleiterspeicheranordnung zum Ausgeben von Datenbits durch eine kleine Anzahl von Datenleitungen

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE69430076T Expired - Lifetime DE69430076T2 (de) 1993-04-02 1994-03-30 Halbleiterspeicher und Zugriffverfahren für solchen Speicher

Country Status (5)

Country Link
US (2) US5426606A (de)
EP (2) EP0618585B1 (de)
JP (1) JPH06290582A (de)
KR (1) KR0160360B1 (de)
DE (2) DE69430076T2 (de)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9405914D0 (en) 1994-03-24 1994-05-11 Discovision Ass Video decompression
US6435737B1 (en) 1992-06-30 2002-08-20 Discovision Associates Data pipeline system and data encoding method
US6034674A (en) * 1992-06-30 2000-03-07 Discovision Associates Buffer manager
US5861894A (en) 1993-06-24 1999-01-19 Discovision Associates Buffer manager
JPH07122099A (ja) * 1993-10-29 1995-05-12 Nec Corp 半導体メモリ
JP2734957B2 (ja) * 1993-12-24 1998-04-02 日本電気株式会社 半導体記憶回路の制御方法
CA2145361C (en) 1994-03-24 1999-09-07 Martin William Sotheran Buffer manager
EP0683457A1 (de) * 1994-05-20 1995-11-22 Advanced Micro Devices, Inc. Computersystem mit einer Snoopsteuerschaltung
JP3157681B2 (ja) * 1994-06-27 2001-04-16 日本電気株式会社 論理データ入力ラッチ回路
JP2982618B2 (ja) * 1994-06-28 1999-11-29 日本電気株式会社 メモリ選択回路
US5610864A (en) 1994-12-23 1997-03-11 Micron Technology, Inc. Burst EDO memory device with maximized write cycle timing
US6525971B2 (en) 1995-06-30 2003-02-25 Micron Technology, Inc. Distributed write data drivers for burst access memories
US6804760B2 (en) * 1994-12-23 2004-10-12 Micron Technology, Inc. Method for determining a type of memory present in a system
US5526320A (en) 1994-12-23 1996-06-11 Micron Technology Inc. Burst EDO memory device
JPH0963262A (ja) * 1995-08-17 1997-03-07 Fujitsu Ltd シンクロナスｄｒａｍ
JP2907074B2 (ja) * 1995-08-25 1999-06-21 日本電気株式会社 半導体記憶装置
KR100192573B1 (ko) * 1995-09-18 1999-06-15 윤종용 멀티 뱅크 구조의 반도체 메모리 장치
JP2991094B2 (ja) * 1995-09-19 1999-12-20 日本電気株式会社 半導体記憶装置
US6035369A (en) 1995-10-19 2000-03-07 Rambus Inc. Method and apparatus for providing a memory with write enable information
JPH09161471A (ja) * 1995-12-06 1997-06-20 Internatl Business Mach Corp <Ibm> Ｄｒａｍシステム、ｄｒａｍシステムの動作方法
US5715476A (en) * 1995-12-29 1998-02-03 Intel Corporation Method and apparatus for controlling linear and toggle mode burst access sequences using toggle mode increment logic
US7681005B1 (en) 1996-01-11 2010-03-16 Micron Technology, Inc. Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation
US5838631A (en) 1996-04-19 1998-11-17 Integrated Device Technology, Inc. Fully synchronous pipelined ram
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
JPH09320269A (ja) * 1996-05-31 1997-12-12 Nippon Steel Corp アドレス装置
US6009038A (en) * 1996-05-31 1999-12-28 United Microelectronics Corporation Addressing unit
KR980004988A (ko) * 1996-06-26 1998-03-30 김광호 버스트 카운터
US6981126B1 (en) 1996-07-03 2005-12-27 Micron Technology, Inc. Continuous interleave burst access
US6401186B1 (en) 1996-07-03 2002-06-04 Micron Technology, Inc. Continuous burst memory which anticipates a next requested start address
JPH1050958A (ja) * 1996-08-05 1998-02-20 Toshiba Corp 半導体記憶装置、半導体記憶装置のレイアウト方法、半導体記憶装置の動作方法および半導体記憶装置の回路配置パターン
US5784329A (en) * 1997-01-13 1998-07-21 Mitsubishi Semiconductor America, Inc. Latched DRAM write bus for quickly clearing DRAM array with minimum power usage
US5870347A (en) 1997-03-11 1999-02-09 Micron Technology, Inc. Multi-bank memory input/output line selection
US6014759A (en) 1997-06-13 2000-01-11 Micron Technology, Inc. Method and apparatus for transferring test data from a memory array
US6044429A (en) 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
EP1895538A1 (de) * 1997-10-10 2008-03-05 Rambus, Inc. Vorrichtung und Verfahren für geleitete Speicherbetriebe
US7103742B1 (en) 1997-12-03 2006-09-05 Micron Technology, Inc. Burst/pipelined edo memory device
JP3204384B2 (ja) 1997-12-10 2001-09-04 エヌイーシーマイクロシステム株式会社 半導体記憶回路
US6115320A (en) 1998-02-23 2000-09-05 Integrated Device Technology, Inc. Separate byte control on fully synchronous pipelined SRAM
CA2233789C (en) * 1998-04-01 2013-06-11 Ian Mes Semiconductor memory asynchronous pipeline
DE69923769T2 (de) * 1998-04-01 2006-02-02 Mosaid Technologies Incorporated, Kanata Asynchrones halbleiterspeicher-fliessband
US6405280B1 (en) 1998-06-05 2002-06-11 Micron Technology, Inc. Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence
US6279071B1 (en) 1998-07-07 2001-08-21 Mitsubishi Electric And Electronics Usa, Inc. System and method for column access in random access memories
JP4748828B2 (ja) * 1999-06-22 2011-08-17 ルネサスエレクトロニクス株式会社 半導体記憶装置
US6278633B1 (en) 1999-11-05 2001-08-21 Multi Level Memory Technology High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations
CN1307647C (zh) 2000-07-07 2007-03-28 睦塞德技术公司 动态随机存取存储器、存储器器件及其执行读命令的方法
JP2002245779A (ja) * 2001-02-20 2002-08-30 Nec Microsystems Ltd 半導体記憶装置
US20040148226A1 (en) * 2003-01-28 2004-07-29 Shanahan Michael E. Method and apparatus for electronic product information and business transactions
KR100535102B1 (ko) * 2003-05-23 2005-12-07 주식회사 하이닉스반도체 컬럼 어드레스 전송 구조 및 방법
KR100546339B1 (ko) * 2003-07-04 2006-01-26 삼성전자주식회사 차동 데이터 스트로빙 모드와 데이터 반전 스킴을 가지는단일 데이터 스트로빙 모드를 선택적으로 구현할 수 있는반도체 장치
KR100532471B1 (ko) * 2003-09-26 2005-12-01 삼성전자주식회사 입출력 데이터 위스 조절이 가능한 메모리 장치 및 그위스 조절 방법
KR100560773B1 (ko) * 2003-10-09 2006-03-13 삼성전자주식회사 동작 모드의 재설정없이 버스트 길이를 제어할 수 있는반도체 메모리 장치 및 그것을 포함하는 메모리 시스템
US20090097301A1 (en) * 2005-06-01 2009-04-16 Matsushita Electric Industrial Co., Ltd. Semiconductor storage apparatus and semiconductor integrated circuit incorporating the same
KR100615580B1 (ko) * 2005-07-05 2006-08-25 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 데이터 입출력 방법과이를 구비한 메모리 시스템
KR100666182B1 (ko) * 2006-01-02 2007-01-09 삼성전자주식회사 이웃하는 워드라인들이 비연속적으로 어드레싱되는 반도체메모리 장치 및 워드라인 어드레싱 방법
KR100761848B1 (ko) * 2006-06-09 2007-09-28 삼성전자주식회사 반도체 장치에서의 데이터 출력장치 및 방법
JP2011034629A (ja) * 2009-07-31 2011-02-17 Elpida Memory Inc 半導体装置
US9330735B2 (en) 2011-07-27 2016-05-03 Rambus Inc. Memory with deferred fractional row activation
JP5972549B2 (ja) 2011-09-29 2016-08-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
KR101983286B1 (ko) 2018-11-05 2019-05-28 선진테크 주식회사 적설량 측정 장치 및 그 구동방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS621182A (ja) * 1985-06-26 1987-01-07 Hitachi Ltd 半導体記憶装置
JPH0760600B2 (ja) * 1987-08-19 1995-06-28 三菱電機株式会社 同期型記憶装置
US5093809A (en) * 1989-04-21 1992-03-03 Siemens Aktiengesellschaft Static memory having pipeline registers
JPH0814989B2 (ja) * 1989-05-09 1996-02-14 日本電気株式会社 内部同期型スタティックｒａｍ
KR100214435B1 (ko) * 1990-07-25 1999-08-02 사와무라 시코 동기식 버스트 엑세스 메모리
US5253212A (en) * 1990-12-01 1993-10-12 Hitachi, Ltd. Semiconductor memory IC and semiconductor memory device
US5319759A (en) * 1991-04-22 1994-06-07 Acer Incorporated Burst address sequence generator
JP2830594B2 (ja) * 1992-03-26 1998-12-02 日本電気株式会社 半導体メモリ装置

Also Published As

Publication number Publication date
DE69411428D1 (de) 1998-08-13
EP0840324B1 (de) 2002-03-06
USRE35934E (en) 1998-10-27
KR0160360B1 (ko) 1999-02-01
EP0618585B1 (de) 1998-07-08
EP0840324A2 (de) 1998-05-06
DE69430076D1 (de) 2002-04-11
EP0840324A3 (de) 1998-12-09
DE69430076T2 (de) 2002-11-14
US5426606A (en) 1995-06-20
EP0618585A3 (de) 1994-12-14
JPH06290582A (ja) 1994-10-18
EP0618585A2 (de) 1994-10-05

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Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

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