DE69224709D1 - Halbleiteranordnung mit verbesserter Durchbruchspannungs-Charakteristik - Google Patents

Halbleiteranordnung mit verbesserter Durchbruchspannungs-Charakteristik

Info

Publication number
DE69224709D1
DE69224709D1 DE69224709T DE69224709T DE69224709D1 DE 69224709 D1 DE69224709 D1 DE 69224709D1 DE 69224709 T DE69224709 T DE 69224709T DE 69224709 T DE69224709 T DE 69224709T DE 69224709 D1 DE69224709 D1 DE 69224709D1
Authority
DE
Germany
Prior art keywords
semiconductor device
breakdown voltage
voltage characteristics
improved breakdown
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69224709T
Other languages
English (en)
Other versions
DE69224709T2 (de
Inventor
Vladimir Nmi Rumennik
Robert W Busse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Power Integrations Inc
Original Assignee
Power Integrations Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Power Integrations Inc filed Critical Power Integrations Inc
Application granted granted Critical
Publication of DE69224709D1 publication Critical patent/DE69224709D1/de
Publication of DE69224709T2 publication Critical patent/DE69224709T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41758Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69224709T 1991-12-12 1992-11-25 Halbleiteranordnung mit verbesserter Durchbruchspannungs-Charakteristik Expired - Lifetime DE69224709T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/808,024 US5258636A (en) 1991-12-12 1991-12-12 Narrow radius tips for high voltage semiconductor devices with interdigitated source and drain electrodes

Publications (2)

Publication Number Publication Date
DE69224709D1 true DE69224709D1 (de) 1998-04-16
DE69224709T2 DE69224709T2 (de) 1998-10-29

Family

ID=25197683

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69224709T Expired - Lifetime DE69224709T2 (de) 1991-12-12 1992-11-25 Halbleiteranordnung mit verbesserter Durchbruchspannungs-Charakteristik

Country Status (4)

Country Link
US (1) US5258636A (de)
EP (1) EP0546377B1 (de)
JP (1) JP2781504B2 (de)
DE (1) DE69224709T2 (de)

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DE69505348T2 (de) * 1995-02-21 1999-03-11 St Microelectronics Srl Hochspannungs-MOSFET mit Feldplatten-Elektrode und Verfahren zur Herstellung
JP3356586B2 (ja) * 1995-06-01 2002-12-16 日本電気株式会社 高耐圧横型mosfet半導体装置
JP3228093B2 (ja) * 1995-06-28 2001-11-12 富士電機株式会社 高耐圧ic
DE69533134T2 (de) 1995-10-30 2005-07-07 Stmicroelectronics S.R.L., Agrate Brianza Leistungsbauteil hoher Dichte in MOS-Technologie
DE69534919T2 (de) 1995-10-30 2007-01-25 Stmicroelectronics S.R.L., Agrate Brianza Leistungsvorrichtung in MOS-Technologie mit einer einzigen kritischen Größe
JP2755247B2 (ja) * 1996-02-28 1998-05-20 日本電気株式会社 半導体装置
US6800903B2 (en) * 1996-11-05 2004-10-05 Power Integrations, Inc. High-voltage transistor with multi-layer conduction region
US6207994B1 (en) 1996-11-05 2001-03-27 Power Integrations, Inc. High-voltage transistor with multi-layer conduction region
US6168983B1 (en) 1996-11-05 2001-01-02 Power Integrations, Inc. Method of making a high-voltage transistor with multiple lateral conduction layers
DE19654113A1 (de) * 1996-12-23 1998-06-25 Asea Brown Boveri Verfahren zum Herstellen eines MOS-gesteuerten Leistungshalbleiterbauelements
TW400560B (en) * 1996-12-23 2000-08-01 Koninkl Philips Electronics Nv Semiconductor device
JP3142057B2 (ja) * 1997-11-13 2001-03-07 日本電気株式会社 半導体装置とその製造方法、及び駆動装置
EP0961325B1 (de) * 1998-05-26 2008-05-07 STMicroelectronics S.r.l. MOS-Technologie-Leistungsanordnung mit hoher Integrationsdichte
US6084277A (en) * 1999-02-18 2000-07-04 Power Integrations, Inc. Lateral power MOSFET with improved gate design
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US6555873B2 (en) * 2001-09-07 2003-04-29 Power Integrations, Inc. High-voltage lateral transistor with a multi-layered extended drain structure
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US6903421B1 (en) 2004-01-16 2005-06-07 System General Corp. Isolated high-voltage LDMOS transistor having a split well structure
JP4342498B2 (ja) * 2005-09-30 2009-10-14 パナソニック株式会社 横型半導体デバイス
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US7589393B2 (en) * 2006-07-25 2009-09-15 System General Corporation Semiconductor structure of a high side driver for two high voltage nodes with partially linked deep wells and method for manufacturing the same
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US7859037B2 (en) 2007-02-16 2010-12-28 Power Integrations, Inc. Checkerboarded high-voltage vertical transistor layout
US8653583B2 (en) 2007-02-16 2014-02-18 Power Integrations, Inc. Sensing FET integrated with a high-voltage transistor
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US7875962B2 (en) * 2007-10-15 2011-01-25 Power Integrations, Inc. Package for a power semiconductor device
JP5150389B2 (ja) * 2008-07-01 2013-02-20 シャープ株式会社 半導体装置
US7960786B2 (en) * 2008-07-09 2011-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Breakdown voltages of ultra-high voltage devices by forming tunnels
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JP5586546B2 (ja) * 2011-03-23 2014-09-10 株式会社東芝 半導体装置
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Also Published As

Publication number Publication date
DE69224709T2 (de) 1998-10-29
US5258636A (en) 1993-11-02
JPH05259454A (ja) 1993-10-08
EP0546377B1 (de) 1998-03-11
EP0546377A2 (de) 1993-06-16
EP0546377A3 (en) 1993-09-29
JP2781504B2 (ja) 1998-07-30

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