DE69427214D1 - Halbleiterspeicheranordnung mit Spannung-Erhöhungsschaltung - Google Patents

Halbleiterspeicheranordnung mit Spannung-Erhöhungsschaltung

Info

Publication number
DE69427214D1
DE69427214D1 DE69427214T DE69427214T DE69427214D1 DE 69427214 D1 DE69427214 D1 DE 69427214D1 DE 69427214 T DE69427214 T DE 69427214T DE 69427214 T DE69427214 T DE 69427214T DE 69427214 D1 DE69427214 D1 DE 69427214D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
boost circuit
voltage boost
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69427214T
Other languages
English (en)
Other versions
DE69427214T2 (de
Inventor
Tetsuya Kaneko
Takashi Ohsawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=26455026&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE69427214(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69427214D1 publication Critical patent/DE69427214D1/de
Application granted granted Critical
Publication of DE69427214T2 publication Critical patent/DE69427214T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69427214T 1993-09-10 1994-09-07 Halbleiterspeicheranordnung mit Spannung-Erhöhungsschaltung Expired - Lifetime DE69427214T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP22533693 1993-09-10
JP6116761A JPH07130175A (ja) 1993-09-10 1994-05-30 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69427214D1 true DE69427214D1 (de) 2001-06-21
DE69427214T2 DE69427214T2 (de) 2001-10-11

Family

ID=26455026

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69427214T Expired - Lifetime DE69427214T2 (de) 1993-09-10 1994-09-07 Halbleiterspeicheranordnung mit Spannung-Erhöhungsschaltung

Country Status (4)

Country Link
US (3) US5689461A (de)
EP (1) EP0643393B1 (de)
JP (1) JPH07130175A (de)
DE (1) DE69427214T2 (de)

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JP3199987B2 (ja) * 1995-08-31 2001-08-20 株式会社東芝 半導体集積回路装置およびその動作検証方法
IT1286072B1 (it) * 1996-10-31 1998-07-07 Sgs Thomson Microelectronics Equalizzatore autoregolato,in particolare per amplificatore di rilevamento,o sense amplifier
KR100226491B1 (ko) * 1996-12-28 1999-10-15 김영환 반도체 메모리에서 비트라인 감지 증폭기의 풀업/풀다운 전압제 공을 위한 디바이스 및 그 구성 방법
TW419828B (en) 1997-02-26 2001-01-21 Toshiba Corp Semiconductor integrated circuit
JPH10261946A (ja) * 1997-03-19 1998-09-29 Mitsubishi Electric Corp 半導体集積回路
FR2762435B1 (fr) * 1997-04-16 2000-12-08 Sgs Thomson Microelectronics Circuit de lecture de memoire avec dispositif de precharge a commande dynamique
JP3399787B2 (ja) * 1997-06-27 2003-04-21 富士通株式会社 半導体記憶装置
US5862089A (en) * 1997-08-14 1999-01-19 Micron Technology, Inc. Method and memory device for dynamic cell plate sensing with ac equilibrate
US5875141A (en) * 1997-08-14 1999-02-23 Micron Technology, Inc. Circuit and method for a memory device with P-channel isolation gates
KR100261217B1 (ko) * 1997-11-21 2000-07-01 윤종용 반도체 메모리장치의 셀 어레이 제어장치
JP4226686B2 (ja) * 1998-05-07 2009-02-18 株式会社東芝 半導体メモリシステム及び半導体メモリのアクセス制御方法及び半導体メモリ
JP2000195268A (ja) * 1998-10-19 2000-07-14 Toshiba Corp 半導体記憶装置
JP4413293B2 (ja) * 1998-09-24 2010-02-10 富士通マイクロエレクトロニクス株式会社 リセット動作を高速化したメモリデバイス
JP2000298984A (ja) * 1999-04-15 2000-10-24 Oki Electric Ind Co Ltd 半導体記憶装置
US6741104B2 (en) * 1999-05-26 2004-05-25 Micron Technology, Inc. DRAM sense amplifier for low voltages
KR100318321B1 (ko) * 1999-06-08 2001-12-22 김영환 반도체 메모리의 비트 라인 균등화 신호 제어회로
US6392472B1 (en) * 1999-06-18 2002-05-21 Mitsubishi Denki Kabushiki Kaisha Constant internal voltage generation circuit
JP4011248B2 (ja) * 1999-12-22 2007-11-21 沖電気工業株式会社 半導体記憶装置
JP3872927B2 (ja) * 2000-03-22 2007-01-24 株式会社東芝 昇圧回路
JP2001283592A (ja) * 2000-03-30 2001-10-12 Nec Corp 半導体記憶装置およびその駆動方法
US6285612B1 (en) * 2000-06-26 2001-09-04 International Business Machines Corporation Reduced bit line equalization level sensing scheme
JP2002133869A (ja) 2000-10-30 2002-05-10 Mitsubishi Electric Corp 半導体記憶装置
KR100395877B1 (ko) * 2000-11-10 2003-08-25 삼성전자주식회사 반도체 메모리의 데이타 감지 장치
KR100413065B1 (ko) * 2001-01-04 2003-12-31 삼성전자주식회사 반도체 메모리 장치의 비트 라인 부스팅 커패시터의 배치구조
JP2002245797A (ja) * 2001-02-16 2002-08-30 Mitsubishi Electric Corp 半導体集積回路
JP4742429B2 (ja) * 2001-02-19 2011-08-10 住友電気工業株式会社 ガラス微粒子堆積体の製造方法
US20030167211A1 (en) * 2002-03-04 2003-09-04 Marco Scibora Method and apparatus for digitally marking media content
US7148699B1 (en) * 2002-06-24 2006-12-12 Rambus Inc. Technique for calibrating electronic devices
US7333378B2 (en) * 2002-09-18 2008-02-19 Samsung Electronics Co., Ltd Memory device that recycles a signal charge
KR100517549B1 (ko) * 2002-09-18 2005-09-28 삼성전자주식회사 차아지 재사용 방법을 이용하는 비트라인 이퀄라이징 전압발생부를 갖는 메모리 장치
US7245549B2 (en) 2003-03-14 2007-07-17 Fujitsu Limited Semiconductor memory device and method of controlling the semiconductor memory device
WO2004081945A1 (ja) * 2003-03-14 2004-09-23 Fujitsu Limited 半導体記憶装置、および半導体記憶装置の制御方法
US6693480B1 (en) 2003-03-27 2004-02-17 Pericom Semiconductor Corp. Voltage booster with increased voltage boost using two pumping capacitors
KR100594227B1 (ko) * 2003-06-19 2006-07-03 삼성전자주식회사 피크 전류가 감소된 인버터를 가지는 저전력 저잡음 비교기
KR100562654B1 (ko) * 2004-04-20 2006-03-20 주식회사 하이닉스반도체 균등화신호(ｂｌｅｑ) 구동회로 및 이를 사용한 반도체메모리 소자
US7221605B2 (en) * 2004-08-31 2007-05-22 Micron Technology, Inc. Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets
US7176719B2 (en) * 2004-08-31 2007-02-13 Micron Technology, Inc. Capacitively-coupled level restore circuits for low voltage swing logic circuits
US7236415B2 (en) * 2004-09-01 2007-06-26 Micron Technology, Inc. Sample and hold memory sense amplifier
KR100642631B1 (ko) 2004-12-06 2006-11-10 삼성전자주식회사 전압 발생회로 및 이를 구비한 반도체 메모리 장치
US7269079B2 (en) * 2005-05-16 2007-09-11 Micron Technology, Inc. Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
JP2007060544A (ja) * 2005-08-26 2007-03-08 Micron Technol Inc 温度係数が小さいパワー・オン・リセットを生成する方法及び装置
JP2007058772A (ja) * 2005-08-26 2007-03-08 Micron Technol Inc バンド・ギャップ基準から可変出力電圧を生成する方法及び装置
JP2007059024A (ja) * 2005-08-26 2007-03-08 Micron Technol Inc 温度補償された読み出し・検証動作をフラッシュ・メモリにおいて生成するための方法及び装置
US7489556B2 (en) * 2006-05-12 2009-02-10 Micron Technology, Inc. Method and apparatus for generating read and verify operations in non-volatile memories
CN101110260B (zh) * 2007-07-10 2010-05-19 中国人民解放军国防科学技术大学 带充电补偿结构的存储器选择性预充电电路
CN101682325B (zh) * 2008-02-27 2013-06-05 松下电器产业株式会社 半导体集成电路以及包括该半导体集成电路的各种装置
JP5465919B2 (ja) * 2009-05-14 2014-04-09 ルネサスエレクトロニクス株式会社 半導体集積装置
JP2010287272A (ja) * 2009-06-10 2010-12-24 Elpida Memory Inc 半導体装置
US8107305B2 (en) * 2009-06-25 2012-01-31 Micron Technology, Inc. Integrated circuit memory operation apparatus and methods
CN101930795B (zh) * 2009-06-25 2014-04-16 上海华虹宏力半导体制造有限公司 位线预处理存储装置及方法
KR101828872B1 (ko) 2011-05-23 2018-02-14 삼성전자주식회사 반도체 메모리 디바이스
CN102436847B (zh) * 2011-09-15 2014-04-02 黑龙江大学 Pmos管带通-带阻和高通-低通变阈电路
CN102426855B (zh) * 2011-10-24 2014-04-02 黑龙江大学 嵌入dram存储矩阵的8值存储单元的8值信息刷新方法及相关电路
JP5710681B2 (ja) * 2013-04-19 2015-04-30 ルネサスエレクトロニクス株式会社 半導体集積装置
KR20210015209A (ko) * 2019-08-01 2021-02-10 에스케이하이닉스 주식회사 데이터 라인 스위칭 제어회로 및 이를 포함하는 반도체 장치
CN115565561B (zh) * 2021-07-02 2024-05-03 长鑫存储技术有限公司 读出电路结构

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JPS58181319A (ja) * 1982-04-19 1983-10-24 Hitachi Ltd タイミング発生回路
JPS58185091A (ja) * 1982-04-24 1983-10-28 Toshiba Corp 昇圧電圧出力回路および昇圧電圧出力回路を備えたアドレスデコ−ド回路
US5268871A (en) * 1991-10-03 1993-12-07 International Business Machines Corporation Power supply tracking regulator for a memory array
JPH05182461A (ja) * 1992-01-07 1993-07-23 Nec Corp 半導体メモリ装置
US5257232A (en) * 1992-03-05 1993-10-26 International Business Machines Corporation Sensing circuit for semiconductor memory with limited bitline voltage swing
US5317212A (en) * 1993-03-19 1994-05-31 Wahlstrom Sven E Dynamic control of configurable logic
JP3364523B2 (ja) * 1993-05-31 2003-01-08 三菱電機株式会社 半導体装置

Also Published As

Publication number Publication date
JPH07130175A (ja) 1995-05-19
US5828611A (en) 1998-10-27
EP0643393B1 (de) 2001-05-16
EP0643393A3 (de) 1995-05-17
US6069828A (en) 2000-05-30
DE69427214T2 (de) 2001-10-11
EP0643393A2 (de) 1995-03-15
US5689461A (en) 1997-11-18

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Legal Events

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8364 No opposition during term of opposition