DE69225537D1 - Integrierte Speicherschaltung - Google Patents
Integrierte SpeicherschaltungInfo
- Publication number
- DE69225537D1 DE69225537D1 DE69225537T DE69225537T DE69225537D1 DE 69225537 D1 DE69225537 D1 DE 69225537D1 DE 69225537 T DE69225537 T DE 69225537T DE 69225537 T DE69225537 T DE 69225537T DE 69225537 D1 DE69225537 D1 DE 69225537D1
- Authority
- DE
- Germany
- Prior art keywords
- memory circuit
- integrated memory
- integrated
- circuit
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Static Random-Access Memory (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/731,802 US5287322A (en) | 1991-07-17 | 1991-07-17 | Integrated circuit dual-port memory device having reduced capacitance |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69225537D1 true DE69225537D1 (de) | 1998-06-25 |
DE69225537T2 DE69225537T2 (de) | 1998-10-22 |
Family
ID=24941003
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69225537T Expired - Fee Related DE69225537T2 (de) | 1991-07-17 | 1992-07-16 | Integrierte Speicherschaltung |
Country Status (4)
Country | Link |
---|---|
US (1) | US5287322A (de) |
EP (1) | EP0523997B1 (de) |
JP (1) | JPH05234376A (de) |
DE (1) | DE69225537T2 (de) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5440506A (en) * | 1992-08-14 | 1995-08-08 | Harris Corporation | Semiconductor ROM device and method |
US5513335A (en) * | 1992-11-02 | 1996-04-30 | Sgs-Thomson Microelectronics, Inc. | Cache tag memory having first and second single-port arrays and a dual-port array |
JP3158017B2 (ja) * | 1994-08-15 | 2001-04-23 | インターナショナル・ビジネス・マシーンズ・コーポレ−ション | 相互結線配列および相互結線配列用の導線を形成する方法 |
KR0150072B1 (ko) * | 1995-11-30 | 1998-10-15 | 양승택 | 병렬처리 컴퓨터 시스템에서의 메모리 데이타 경로 제어장치 |
US20080220776A1 (en) * | 1997-07-30 | 2008-09-11 | Steven Tischer | Interface devices for facilitating communications between devices and communications networks |
US20080195641A1 (en) * | 1997-07-30 | 2008-08-14 | Steven Tischer | Apparatus and method for aggregating and accessing data according to user information |
US20080207197A1 (en) * | 1997-07-30 | 2008-08-28 | Steven Tischer | Apparatus, method, and computer-readable medium for interfacing devices with communications networks |
US20080207202A1 (en) * | 1997-07-30 | 2008-08-28 | Zellner Samuel N | Apparatus and method for providing a user interface for facilitating communications between devices |
US20080192769A1 (en) * | 1997-07-30 | 2008-08-14 | Steven Tischer | Apparatus and method for prioritizing communications between devices |
US7194083B1 (en) | 2002-07-15 | 2007-03-20 | Bellsouth Intellectual Property Corporation | System and method for interfacing plain old telephone system (POTS) devices with cellular networks |
US7149514B1 (en) | 1997-07-30 | 2006-12-12 | Bellsouth Intellectual Property Corp. | Cellular docking station |
US20080194251A1 (en) * | 1997-07-30 | 2008-08-14 | Steven Tischer | Apparatus and method for providing communications and connection-oriented services to devices |
US5949698A (en) | 1998-02-20 | 1999-09-07 | Micron Technology, Inc. | Twisted global column decoder |
US6249452B1 (en) * | 1998-09-28 | 2001-06-19 | Texas Instruments Incorporated | Semiconductor device having offset twisted bit lines |
US6084820A (en) * | 1999-01-06 | 2000-07-04 | Virage Logic Corporation | Dual port memory device with vertical shielding |
US6411802B1 (en) | 1999-03-15 | 2002-06-25 | Bellsouth Intellectual Property Management Corporation | Wireless backup telephone device |
US6370078B1 (en) * | 2000-03-14 | 2002-04-09 | Lsi Logic Corporation | Way to compensate the effect of coupling between bitlines in a multi-port memories |
US6560160B1 (en) | 2000-11-13 | 2003-05-06 | Agilent Technologies, Inc. | Multi-port memory that sequences port accesses |
DE10124752B4 (de) * | 2001-05-21 | 2006-01-12 | Infineon Technologies Ag | Schaltungsanordnung zum Auslesen und zum Speichern von binären Speicherzellensignalen |
KR100475052B1 (ko) * | 2001-11-26 | 2005-03-10 | 삼성전자주식회사 | 감소된 비트라인 전압 오프셋을 갖는 멀티포트 반도체메모리장치 및 이의 메모리셀 배치방법 |
US7120454B1 (en) * | 2001-12-26 | 2006-10-10 | Bellsouth Intellectual Property Corp. | Auto sensing home base station for mobile telephone with remote answering capabilites |
US6498758B1 (en) * | 2002-01-16 | 2002-12-24 | Lsi Logic Corporation | Twisted bitlines to reduce coupling effects (dual port memories) |
US8543098B2 (en) * | 2002-07-15 | 2013-09-24 | At&T Intellectual Property I, L.P. | Apparatus and method for securely providing communications between devices and networks |
US8554187B2 (en) * | 2002-07-15 | 2013-10-08 | At&T Intellectual Property I, L.P. | Apparatus and method for routing communications between networks and devices |
US8275371B2 (en) | 2002-07-15 | 2012-09-25 | At&T Intellectual Property I, L.P. | Apparatus and method for providing communications and connection-oriented services to devices |
US7200424B2 (en) * | 2002-07-15 | 2007-04-03 | Bellsouth Intelectual Property Corporation | Systems and methods for restricting the use and movement of telephony devices |
US8526466B2 (en) | 2002-07-15 | 2013-09-03 | At&T Intellectual Property I, L.P. | Apparatus and method for prioritizing communications between devices |
US8416804B2 (en) | 2002-07-15 | 2013-04-09 | At&T Intellectual Property I, L.P. | Apparatus and method for providing a user interface for facilitating communications between devices |
US8000682B2 (en) * | 2002-07-15 | 2011-08-16 | At&T Intellectual Property I, L.P. | Apparatus and method for restricting access to data |
US6909663B1 (en) | 2003-09-26 | 2005-06-21 | Lattice Semiconductor Corporation | Multiport memory with twisted bitlines |
FR2881565B1 (fr) * | 2005-02-03 | 2007-08-24 | Atmel Corp | Circuits de selection de ligne binaire pour memoires non volatiles |
US7286438B2 (en) * | 2005-04-12 | 2007-10-23 | Integrated Device Technology, Inc. | Dual port memory cell with reduced coupling capacitance and small cell size |
US7414913B1 (en) * | 2005-08-01 | 2008-08-19 | Lattice Semiconductor Corporation | Bitline twisting scheme for multiport memory |
US8179708B2 (en) * | 2009-02-18 | 2012-05-15 | Atmel Corporation | Anti-cross-talk circuitry for ROM arrays |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4870619A (en) * | 1986-10-14 | 1989-09-26 | Monolithic Systems Corp. | Memory chip array with inverting and non-inverting address drivers |
JPS63153792A (ja) * | 1986-12-17 | 1988-06-27 | Sharp Corp | 半導体メモリ装置 |
JPH07105134B2 (ja) * | 1987-08-28 | 1995-11-13 | 三菱電機株式会社 | 半導体記憶装置 |
KR970003710B1 (ko) * | 1987-09-04 | 1997-03-21 | 미다 가쓰시게 | 저잡음 반도체 메모리 |
JPH01143094A (ja) * | 1987-11-28 | 1989-06-05 | Mitsubishi Electric Corp | 半導体記憶装置 |
US5144583A (en) * | 1989-01-09 | 1992-09-01 | Kabushiki Kaisha Toshiba | Dynamic semiconductor memory device with twisted bit-line structure |
JPH0372674A (ja) * | 1989-04-28 | 1991-03-27 | Nec Corp | 半導体記憶装置 |
JPH02302986A (ja) * | 1989-05-16 | 1990-12-14 | Mitsubishi Electric Corp | ダイナミック型半導体記憶装置 |
JP2982905B2 (ja) * | 1989-10-02 | 1999-11-29 | 三菱電機株式会社 | ダイナミック型半導体記憶装置 |
KR930001737B1 (ko) * | 1989-12-29 | 1993-03-12 | 삼성전자 주식회사 | 반도체 메모리 어레이의 워드라인 배열방법 |
US5339322A (en) * | 1991-03-29 | 1994-08-16 | Sgs-Thomson Microelectronics, Inc. | Cache tag parity detect circuit |
-
1991
- 1991-07-17 US US07/731,802 patent/US5287322A/en not_active Expired - Lifetime
-
1992
- 1992-07-16 DE DE69225537T patent/DE69225537T2/de not_active Expired - Fee Related
- 1992-07-16 EP EP92306528A patent/EP0523997B1/de not_active Expired - Lifetime
- 1992-07-17 JP JP4190422A patent/JPH05234376A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPH05234376A (ja) | 1993-09-10 |
EP0523997B1 (de) | 1998-05-20 |
DE69225537T2 (de) | 1998-10-22 |
EP0523997A1 (de) | 1993-01-20 |
US5287322A (en) | 1994-02-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |