DE69221218T2 - Halbleiterspeicher - Google Patents

Halbleiterspeicher

Info

Publication number
DE69221218T2
DE69221218T2 DE69221218T DE69221218T DE69221218T2 DE 69221218 T2 DE69221218 T2 DE 69221218T2 DE 69221218 T DE69221218 T DE 69221218T DE 69221218 T DE69221218 T DE 69221218T DE 69221218 T2 DE69221218 T2 DE 69221218T2
Authority
DE
Germany
Prior art keywords
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69221218T
Other languages
English (en)
Other versions
DE69221218D1 (de
Inventor
Masaru Nawaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE69221218D1 publication Critical patent/DE69221218D1/de
Application granted granted Critical
Publication of DE69221218T2 publication Critical patent/DE69221218T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
DE69221218T 1991-06-21 1992-02-17 Halbleiterspeicher Expired - Lifetime DE69221218T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3150551A JPH04372790A (ja) 1991-06-21 1991-06-21 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69221218D1 DE69221218D1 (de) 1997-09-04
DE69221218T2 true DE69221218T2 (de) 1998-02-05

Family

ID=15499352

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69221218T Expired - Lifetime DE69221218T2 (de) 1991-06-21 1992-02-17 Halbleiterspeicher

Country Status (4)

Country Link
US (1) US5295109A (de)
EP (1) EP0519584B1 (de)
JP (1) JPH04372790A (de)
DE (1) DE69221218T2 (de)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3001342B2 (ja) * 1993-02-10 2000-01-24 日本電気株式会社 記憶装置
JP2988804B2 (ja) * 1993-03-19 1999-12-13 株式会社東芝 半導体メモリ装置
JPH07153266A (ja) * 1993-11-26 1995-06-16 Mitsubishi Electric Corp Ｄｒａｍ制御回路
US5450364A (en) * 1994-01-31 1995-09-12 Texas Instruments Incorporated Method and apparatus for production testing of self-refresh operations and a particular application to synchronous memory devices
US6392948B1 (en) * 1996-08-29 2002-05-21 Micron Technology, Inc. Semiconductor device with self refresh test mode
US6359815B1 (en) * 1998-03-12 2002-03-19 Hitachi, Ltd. Data transmitter
JPH11345486A (ja) * 1998-06-01 1999-12-14 Mitsubishi Electric Corp セルフ・リフレッシュ制御回路を備えたｄｒａｍおよびシステムｌｓｉ
US5999474A (en) 1998-10-01 1999-12-07 Monolithic System Tech Inc Method and apparatus for complete hiding of the refresh of a semiconductor memory
US6707743B2 (en) 1998-10-01 2004-03-16 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division
US6504780B2 (en) 1998-10-01 2003-01-07 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a dram device using clock division
US6415353B1 (en) 1998-10-01 2002-07-02 Monolithic System Technology, Inc. Read/write buffers for complete hiding of the refresh of a semiconductor memory and method of operating same
US6370073B2 (en) 1998-10-01 2002-04-09 Monlithic System Technology, Inc. Single-port multi-bank memory system having read and write buffers and method of operating same
US6898140B2 (en) 1998-10-01 2005-05-24 Monolithic System Technology, Inc. Method and apparatus for temperature adaptive refresh in 1T-SRAM compatible memory using the subthreshold characteristics of MOSFET transistors
KR100364128B1 (ko) * 1999-04-08 2002-12-11 주식회사 하이닉스반도체 셀프리프레쉬 발진주기 측정장치
CN1231918C (zh) * 2000-08-31 2005-12-14 恩益禧电子股份有限公司 半导体存储装置及其测试方法和测试电路
US6643205B2 (en) * 2001-10-23 2003-11-04 Coremagic, Inc. Apparatus and method for refresh and data input device in SRAM having storage capacitor cell
US6981187B1 (en) * 2002-11-06 2005-12-27 Nanoamp Solutions, Inc. Test mode for a self-refreshed SRAM with DRAM memory cells
US6795364B1 (en) * 2003-02-28 2004-09-21 Monolithic System Technology, Inc. Method and apparatus for lengthening the data-retention time of a DRAM device in standby mode
US20050226079A1 (en) * 2004-04-08 2005-10-13 Yiming Zhu Methods and apparatus for dual port memory devices having hidden refresh and double bandwidth
KR100576922B1 (ko) 2004-04-19 2006-05-03 주식회사 하이닉스반도체 고전압 발생 회로
US20060190678A1 (en) * 2005-02-22 2006-08-24 Butler Douglas B Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a single DRAM cache and tag
US7506100B2 (en) * 2005-02-23 2009-03-17 United Memories, Inc. Static random access memory (SRAM) compatible, high availability memory array and method employing synchronous dynamic random access memory (DRAM) in conjunction with a data cache and separate read and write registers and tag blocks
US7532532B2 (en) * 2005-05-31 2009-05-12 Micron Technology, Inc. System and method for hidden-refresh rate modification
US7274618B2 (en) * 2005-06-24 2007-09-25 Monolithic System Technology, Inc. Word line driver for DRAM embedded in a logic process
DE102006020098A1 (de) * 2006-04-29 2007-10-31 Infineon Technologies Ag Speicherschaltung und Verfahren zum Auffrischen von dynamischen Speicherzellen
US7721041B2 (en) * 2007-07-26 2010-05-18 Intel Corporation PSRAM and method for operating thereof
JP5978860B2 (ja) * 2012-08-31 2016-08-24 富士通株式会社 情報処理装置、メモリ制御ユニット、メモリ制御方法および制御プログラム
US9959921B2 (en) * 2016-04-01 2018-05-01 Micron Technology, Inc. Apparatuses and methods for refresh control

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1041882B (it) * 1975-08-20 1980-01-10 Honeywell Inf Systems Memoria dinamica a semiconduttori e relativo sistema di recarica
EP0019150B1 (de) * 1979-05-15 1984-07-18 Mostek Corporation Verfahren und Schaltung zum Prüfen der Arbeitsweise eines internen Regenerierungszählers in einem Speicher mit wahlfreiem Zugriff
JPS5918792B2 (ja) * 1979-07-05 1984-04-28 富士通株式会社 リフレツシユ読取り書込み制御方式
JPS6166295A (ja) * 1984-09-10 1986-04-05 Nec Corp 半導体メモリ
US4747082A (en) * 1984-11-28 1988-05-24 Hitachi Ltd. Semiconductor memory with automatic refresh means
JPS62188095A (ja) * 1986-02-14 1987-08-17 Toshiba Corp 半導体記憶装置の制御回路
JPS6355797A (ja) * 1986-08-27 1988-03-10 Fujitsu Ltd メモリ
JPH01124195A (ja) * 1987-11-09 1989-05-17 Sharp Corp セルフリフレッシュ方式
JPH01194194A (ja) * 1988-01-29 1989-08-04 Nec Ic Microcomput Syst Ltd 半導体メモリ装置
JP2865170B2 (ja) * 1988-07-06 1999-03-08 三菱電機株式会社 電子回路装置

Also Published As

Publication number Publication date
EP0519584A3 (en) 1993-09-22
DE69221218D1 (de) 1997-09-04
EP0519584B1 (de) 1997-07-30
EP0519584A2 (de) 1992-12-23
JPH04372790A (ja) 1992-12-25
US5295109A (en) 1994-03-15

Similar Documents

Publication Publication Date Title
DE69333796D1 (de) Halbleiterspeicher
DE69230810T2 (de) Halbleiterspeicheranordnung
DE69224315T2 (de) Halbleiterspeichervorrichtung
DE69222560D1 (de) Halbleiterfestwertspeicher
DE69221218D1 (de) Halbleiterspeicher
DE69232950D1 (de) Halbleiterspeichervorrichtung
DE69216695D1 (de) Halbleiterspeicher
DE69119800D1 (de) Halbleiterspeicher
DE69129492D1 (de) Halbleiterspeicher
DE69220101D1 (de) Halbleiterspeichereinrichtung
DE69219518D1 (de) Halbleiterspeicheranordnung
DE69223333T2 (de) Halbleiterspeicheranordnung
DE69222793D1 (de) Halbleiterspeicheranordnung
DE69224559D1 (de) Halbleiterspeicher
DE69225298D1 (de) Halbleiterspeichervorrichtung
DE69215555D1 (de) Halbleiterspeicheranordnung
DE69119287D1 (de) Halbleiterspeicher
DE69119920D1 (de) Halbleiterspeicher
DE69327125D1 (de) Halbleiterspeicher
KR940003042A (ko) 반도체 기억장치
DE69222333T2 (de) Halbleiterspeicheranordnung
DE69223857T2 (de) Halbleiterspeicher
DE69227792T2 (de) Halbleiter-Speicheranordnung
DE69215166D1 (de) Halbleiterspeicher
DE69131132D1 (de) Halbleiterspeicheranordnung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition