DE69327125D1 - Halbleiterspeicher - Google Patents

Halbleiterspeicher

Info

Publication number
DE69327125D1
DE69327125D1 DE69327125T DE69327125T DE69327125D1 DE 69327125 D1 DE69327125 D1 DE 69327125D1 DE 69327125 T DE69327125 T DE 69327125T DE 69327125 T DE69327125 T DE 69327125T DE 69327125 D1 DE69327125 D1 DE 69327125D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69327125T
Other languages
English (en)
Other versions
DE69327125T2 (de
Inventor
Yasuhiro Hotta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP4053159A external-priority patent/JP2983750B2/ja
Priority claimed from JP4065736A external-priority patent/JPH05268054A/ja
Priority claimed from JP4281998A external-priority patent/JP2915720B2/ja
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE69327125D1 publication Critical patent/DE69327125D1/de
Publication of DE69327125T2 publication Critical patent/DE69327125T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE69327125T 1992-03-12 1993-03-12 Halbleiterspeicher Expired - Lifetime DE69327125T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP4053159A JP2983750B2 (ja) 1992-03-12 1992-03-12 半導体記憶装置
JP4065736A JPH05268054A (ja) 1992-03-24 1992-03-24 集積回路装置
JP4281998A JP2915720B2 (ja) 1992-10-20 1992-10-20 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69327125D1 true DE69327125D1 (de) 2000-01-05
DE69327125T2 DE69327125T2 (de) 2000-04-20

Family

ID=27294857

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69327125T Expired - Lifetime DE69327125T2 (de) 1992-03-12 1993-03-12 Halbleiterspeicher

Country Status (3)

Country Link
US (1) US5402387A (de)
EP (1) EP0560623B1 (de)
DE (1) DE69327125T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221628A (ja) * 1994-02-08 1995-08-18 Toshiba Corp 入力回路
EP0678870B1 (de) * 1994-02-18 1999-07-28 STMicroelectronics S.r.l. Verfahren und Schaltung zum Unterdrücken von Datenladerauschen in nichtflüchtigen Speichern
DE69421266T2 (de) * 1994-02-18 2000-05-18 St Microelectronics Srl Lesetaktsteuerungsverfahren und Schaltung für nichtflüchtige Speicher
JP3769310B2 (ja) * 1995-04-10 2006-04-26 日本テキサス・インスツルメンツ株式会社 入力回路
KR0179793B1 (ko) * 1995-12-28 1999-04-15 문정환 반도체 메모리의 센스 앰프 출력 제어 회로
US5801548A (en) * 1996-04-11 1998-09-01 Xilinx Inc Configurable performance-optimized programmable logic device
KR100626391B1 (ko) * 2005-04-01 2006-09-20 삼성전자주식회사 원낸드 플래시 메모리 및 그것을 포함한 데이터 처리시스템
US9054578B2 (en) * 2012-06-20 2015-06-09 Mosys, Inc. Hybrid driver including a turbo mode
US8836381B2 (en) 2012-06-20 2014-09-16 Mosys, Inc. Pseudo-supply hybrid driver

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4337525A (en) * 1979-04-17 1982-06-29 Nippon Electric Co., Ltd. Asynchronous circuit responsive to changes in logic level
JPS5794986A (en) * 1980-12-02 1982-06-12 Nec Corp Semiconductor circuit
JPS57147194A (en) * 1981-03-05 1982-09-10 Fujitsu Ltd Address buffer
DE3169127D1 (en) * 1981-05-13 1985-04-04 Ibm Deutschland Input circuit for an integrated monolithic semiconductor memory using field effect transistors
JPH0736272B2 (ja) * 1986-12-24 1995-04-19 株式会社日立製作所 半導体集積回路装置
US5163168A (en) * 1990-03-30 1992-11-10 Matsushita Electric Industrial Co., Ltd. Pulse signal generator and redundancy selection signal generator
JP2530055B2 (ja) * 1990-08-30 1996-09-04 株式会社東芝 半導体集積回路
JP3245605B2 (ja) * 1991-02-15 2002-01-15 独立行政法人産業技術総合研究所 ヒドラジン分解用触媒の製造方法

Also Published As

Publication number Publication date
DE69327125T2 (de) 2000-04-20
EP0560623A2 (de) 1993-09-15
US5402387A (en) 1995-03-28
EP0560623A3 (de) 1994-01-26
EP0560623B1 (de) 1999-12-01

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