DE69331210T2 - Integriertes Speicherschaltungsgerät - Google Patents

Integriertes Speicherschaltungsgerät

Info

Publication number
DE69331210T2
DE69331210T2 DE69331210T DE69331210T DE69331210T2 DE 69331210 T2 DE69331210 T2 DE 69331210T2 DE 69331210 T DE69331210 T DE 69331210T DE 69331210 T DE69331210 T DE 69331210T DE 69331210 T2 DE69331210 T2 DE 69331210T2
Authority
DE
Germany
Prior art keywords
circuit device
memory circuit
integrated memory
integrated
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69331210T
Other languages
English (en)
Other versions
DE69331210D1 (de
Inventor
Yuji Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69331210D1 publication Critical patent/DE69331210D1/de
Application granted granted Critical
Publication of DE69331210T2 publication Critical patent/DE69331210T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE69331210T 1992-08-28 1993-08-27 Integriertes Speicherschaltungsgerät Expired - Fee Related DE69331210T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4230587A JP2975777B2 (ja) 1992-08-28 1992-08-28 集積回路

Publications (2)

Publication Number Publication Date
DE69331210D1 DE69331210D1 (de) 2002-01-10
DE69331210T2 true DE69331210T2 (de) 2002-06-27

Family

ID=16910083

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69331210T Expired - Fee Related DE69331210T2 (de) 1992-08-28 1993-08-27 Integriertes Speicherschaltungsgerät

Country Status (5)

Country Link
US (1) US5428573A (de)
EP (1) EP0584832B1 (de)
JP (1) JP2975777B2 (de)
KR (1) KR970001670B1 (de)
DE (1) DE69331210T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3161254B2 (ja) * 1994-11-25 2001-04-25 株式会社日立製作所 同期式メモリ装置
JPH08221975A (ja) * 1995-02-17 1996-08-30 Toshiba Corp 半導体メモリ回路
US6035369A (en) 1995-10-19 2000-03-07 Rambus Inc. Method and apparatus for providing a memory with write enable information
JPH09293388A (ja) * 1996-04-24 1997-11-11 Toshiba Corp 半導体記憶装置
US6209071B1 (en) 1996-05-07 2001-03-27 Rambus Inc. Asynchronous request/synchronous data dynamic random access memory
KR100200930B1 (ko) * 1996-12-06 1999-06-15 윤종용 버스트 모드동작에 적합한 반도체 메모리 장치의 로우 디코더
JPH117792A (ja) * 1997-06-19 1999-01-12 Mitsubishi Electric Corp 半導体記憶装置
JP2001155485A (ja) * 1999-11-29 2001-06-08 Mitsubishi Electric Corp 半導体記憶装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799616B2 (ja) * 1984-08-30 1995-10-25 三菱電機株式会社 半導体記憶装置
JPH0736269B2 (ja) * 1985-08-30 1995-04-19 株式会社日立製作所 半導体記憶装置
JPS6265300A (ja) * 1985-09-18 1987-03-24 Toshiba Corp 半導体記憶装置
JP2698834B2 (ja) * 1988-11-22 1998-01-19 株式会社日立製作所 不揮発性記憶装置
US5255228A (en) * 1989-01-10 1993-10-19 Matsushita Electronics Corporation Semiconductor memory device with redundancy circuits
DE4118804C2 (de) * 1990-06-08 1996-01-04 Toshiba Kawasaki Kk Serienzugriff-Speicheranordnung

Also Published As

Publication number Publication date
EP0584832B1 (de) 2001-11-28
EP0584832A3 (de) 1998-01-21
DE69331210D1 (de) 2002-01-10
US5428573A (en) 1995-06-27
JP2975777B2 (ja) 1999-11-10
JPH0676564A (ja) 1994-03-18
EP0584832A2 (de) 1994-03-02
KR940004655A (ko) 1994-03-15
KR970001670B1 (ko) 1997-02-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee