DE69118049D1 - Halbleiterspeicheranordnung mit einer Leistungserhöhungsschaltung - Google Patents

Halbleiterspeicheranordnung mit einer Leistungserhöhungsschaltung

Info

Publication number
DE69118049D1
DE69118049D1 DE69118049T DE69118049T DE69118049D1 DE 69118049 D1 DE69118049 D1 DE 69118049D1 DE 69118049 T DE69118049 T DE 69118049T DE 69118049 T DE69118049 T DE 69118049T DE 69118049 D1 DE69118049 D1 DE 69118049D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
boost circuit
power boost
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69118049T
Other languages
English (en)
Other versions
DE69118049T2 (de
Inventor
Atsushi Hatakeyama
Masao Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69118049D1 publication Critical patent/DE69118049D1/de
Application granted granted Critical
Publication of DE69118049T2 publication Critical patent/DE69118049T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
DE69118049T 1990-08-20 1991-08-12 Halbleiterspeicheranordnung mit einer Leistungserhöhungsschaltung Expired - Fee Related DE69118049T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2218731A JPH0812754B2 (ja) 1990-08-20 1990-08-20 昇圧回路

Publications (2)

Publication Number Publication Date
DE69118049D1 true DE69118049D1 (de) 1996-04-25
DE69118049T2 DE69118049T2 (de) 1996-08-01

Family

ID=16724554

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69118049T Expired - Fee Related DE69118049T2 (de) 1990-08-20 1991-08-12 Halbleiterspeicheranordnung mit einer Leistungserhöhungsschaltung

Country Status (5)

Country Link
US (1) US5253204A (de)
EP (1) EP0472095B1 (de)
JP (1) JPH0812754B2 (de)
KR (1) KR950014242B1 (de)
DE (1) DE69118049T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940005509B1 (ko) * 1992-02-14 1994-06-20 삼성전자 주식회사 승압단속회로및이를구비하는출력버퍼회로
DE4324855C1 (de) * 1993-07-23 1994-09-22 Siemens Ag Ladungspumpe
JP2570984B2 (ja) * 1993-10-06 1997-01-16 日本電気株式会社 出力回路
KR960011206B1 (ko) * 1993-11-09 1996-08-21 삼성전자 주식회사 반도체메모리장치의 워드라인구동회로
KR0172850B1 (ko) * 1995-11-23 1999-03-30 문정환 고효율 전하 펌프회로
DE19545558C2 (de) * 1995-12-06 2002-06-27 Infineon Technologies Ag Verfahren zur Ansteuerung eines Feldeffekttransistors
JPH09320267A (ja) * 1996-05-28 1997-12-12 Oki Micro Design Miyazaki:Kk 昇圧回路の駆動方法および昇圧回路
US5805507A (en) * 1996-10-01 1998-09-08 Microchip Technology Incorporated Voltage reference generator for EPROM memory array
DE19651768C1 (de) * 1996-12-12 1998-02-19 Siemens Ag Schaltungsanordnung zur Erzeugung einer erhöhten Ausgangsspannung
US6160749A (en) * 1997-03-14 2000-12-12 Hyundai Electronics America Pump control circuit
US5914908A (en) * 1997-03-14 1999-06-22 Hyundai Electronics America Method of operating a boosted wordline
US6134146A (en) * 1998-10-05 2000-10-17 Advanced Micro Devices Wordline driver for flash electrically erasable programmable read-only memory (EEPROM)
US6430087B1 (en) * 2000-02-28 2002-08-06 Advanced Micro Devices, Inc. Trimming method and system for wordline booster to minimize process variation of boosted wordline voltage
JP4960544B2 (ja) * 2000-07-06 2012-06-27 エルピーダメモリ株式会社 半導体記憶装置及びその制御方法
DE102004063314A1 (de) * 2004-12-23 2006-07-13 Carl Zeiss Smt Ag Filtereinrichtung für die Kompensation einer asymmetrischen Pupillenausleuchtung
US7924633B2 (en) * 2009-02-20 2011-04-12 International Business Machines Corporation Implementing boosted wordline voltage in memories
US7894230B2 (en) 2009-02-24 2011-02-22 Mosaid Technologies Incorporated Stacked semiconductor devices including a master device
JP5398520B2 (ja) * 2009-12-25 2014-01-29 株式会社東芝 ワード線駆動回路
TWI407694B (zh) * 2010-01-27 2013-09-01 Novatek Microelectronics Corp 可抑制電壓過衝之輸出緩衝電路及方法
JP2013198125A (ja) * 2012-03-22 2013-09-30 Fujitsu Semiconductor Ltd 半導体装置
US8729951B1 (en) 2012-11-27 2014-05-20 Freescale Semiconductor, Inc. Voltage ramp-up protection

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5862895A (ja) * 1981-10-12 1983-04-14 Mitsubishi Electric Corp 半導体記憶回路
JPS61294695A (ja) * 1985-06-20 1986-12-25 Mitsubishi Electric Corp 半導体集積回路装置
US5051959A (en) * 1985-08-14 1991-09-24 Fujitsu Limited Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type
JPS6243895A (ja) * 1985-08-20 1987-02-25 Nec Corp 半導体メモリ回路
JPS62197997A (ja) * 1986-02-26 1987-09-01 Hitachi Ltd 半導体記憶装置
JPH0817032B2 (ja) * 1986-03-12 1996-02-21 株式会社日立製作所 半導体集積回路装置
JPS63239673A (ja) * 1987-03-27 1988-10-05 Hitachi Ltd 半導体集積回路装置
EP0367450B1 (de) * 1988-10-31 1994-12-21 Texas Instruments Incorporated Verfahren und Ladungsfesthaltesignal-Erhöhungsschaltung

Also Published As

Publication number Publication date
EP0472095B1 (de) 1996-03-20
JPH04102292A (ja) 1992-04-03
KR920005151A (ko) 1992-03-28
KR950014242B1 (ko) 1995-11-23
US5253204A (en) 1993-10-12
EP0472095A2 (de) 1992-02-26
JPH0812754B2 (ja) 1996-02-07
EP0472095A3 (en) 1992-11-19
DE69118049T2 (de) 1996-08-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee