US5253204A - Semiconductor memory device having a boost circuit - Google Patents

Semiconductor memory device having a boost circuit Download PDF

Info

Publication number
US5253204A
US5253204A US07/747,049 US74704991A US5253204A US 5253204 A US5253204 A US 5253204A US 74704991 A US74704991 A US 74704991A US 5253204 A US5253204 A US 5253204A
Authority
US
United States
Prior art keywords
voltage
word line
mos transistor
gate
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US07/747,049
Other languages
English (en)
Inventor
Atsushi Hatakeyama
Masao Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: HATAKEYAMA, ATSUSHI, NAKANO, MASAO
Priority to CA002075410A priority Critical patent/CA2075410A1/en
Application granted granted Critical
Publication of US5253204A publication Critical patent/US5253204A/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Definitions

  • the present invention generally relates to semiconductor memory devices and, more particularly, to a semiconductor memory device having a boost circuit.
  • reading and writing of data is achieved by addressing a memory cell that in turn is made by selecting a word line and a bit line.
  • a word line voltage which is boosted to a level above the supply voltage level is applied to a selected word line to activate the memory cell transistor that is connected to a selected memory cell, and the voltage change appeared on the selected bit line is detected.
  • the selected word line is boosted and the data on the selected bit line is written into the memory cell.
  • FIG. 1 shows an overall construction of a typical dynamic random access memory (DRAM) device.
  • DRAM dynamic random access memory
  • the device comprises a memory cell array 1 in which a number of memory cells 1a are arranged in rows and columns, wherein the memory cells aligned in the row direction are connected commonly to a word line WL while the memory cells aligned in the column direction are connected commonly to a bit line BL.
  • the word lines are connected to the word decoder 2 and selectively enabled by a row decoder 2 in response to address data ADDRESS that is supplied to an address buffer circuit 3. Thereby, a word line voltage produced by a word line driver 4 is supplied to the selected word line WL via the row decoder 2.
  • the address buffer circuit 3 further produces column address data for specifying a bit line, and the column address data thus produced is supplied to a column decoder 5. There, the column decoder 5 selects the specified bit line BL via an input/output gate 6.
  • the memory cell transistor When reading data, the memory cell transistor is activated for all the memory cells that are connected commonly to a selected word line WL, and a minute voltage change appears in each bit line of the memory cell array 1 according to the content of data that is stored in the memory cell. This voltage change thus appearing on each bit line is detected by a sense amplifier that is included in the input/output gate 6, and the column decoder 5 selectively outputs the voltage change of the selected bit line BL as the output data Dout. The output data is then transferred to an output terminal Dout via an output buffer circuit 7.
  • the word line WL is selected similarly to the case of reading. Further, a write enable signal /WE is supplied to an input buffer circuit 8 via a write clock generator 9 to activate the same. Further, input data Din is supplied to the input buffer circuit 8 thus activated. Thereby, the input data Din is transferred from the buffer circuit 8 to the column decoder 5 and further to a selected bit line BL, and is written into the selected memory cell 1a via the memory cell transistor that is activated by the selection of the word line WL.
  • the foregoing read/write operation is activated in response to the row address strobe signal /RAS and the column address strobe signal /CAS as usual in the DRAM device.
  • the strobe signals /RAS and /CAS are supplied to a clock generator 9 that produces and supplies various control signals to the row decoder 2, address buffer 3, the word line driver 4, the column decoder 5, the input/output gate 6, the output buffer circuit 7, and the input buffer circuit 8.
  • the conventional DRAM device uses a boost circuit in cooperation with the word line driver 4.
  • FIG. 2 shows an example of the conventional word line driver 4 in which a boost circuit 20 is used.
  • the word line driver 4 includes MOS transistors T01, T03 and T04 connected in series, wherein the drain of the MOS transistor T01 is connected to a capacitance that is provided by a MOS transistor T02, at a node N01. More specifically, the drain of the MOS transistor T01 is connected to the gate of the MOS transistor T02 that in turn has its source and drain connected with each other and functions as the capacitor. As will be described later, this transistor T02 acts as the boost circuit for boosting the word line voltage.
  • the source of the MOS transistor T01 is connected to the drain of the MOS transistor T03, and the source of the MOS transistor T03 is connected to the drain of the MOS transistor T04. Further, the source of the transistor T04 is connected to the ground. Thereby, a main word line 14 is connected to the source of the MOS transistor T01.
  • the main word line 18, in turn, is connected to the row decoder 2 of FIG. 1 that includes a number of drive circuits 2A, 2B, . . . . Each of the drive circuits 2A, 2B, . . . is connected to a corresponding word line WL1, WL2, . . . and activates the same selectively in response to the address data supplied thereto from the address buffer circuit 3.
  • MOS transistors T01', T03' and T04' that are connected with each other between the node N01 and the ground.
  • the drain of the transistor T01' is connected to the node N01
  • the source of the transistor T01' is connected to the drain of the transistor T03'
  • the source of the transistor T03' is connected to the drain of the transistor T04'
  • the source of the transistor T04' is connected to the ground.
  • the gate of the transistor T01 and the gate of the transistor T01' are connected commonly to an input terminal to which a control signal ⁇ 1 is supplied from the clock generator 10 of FIG. 1.
  • the gate of the transistor T03 and the gate of the transistor T03' are connected commonly with each other to the power supply terminal for receiving the supply voltage Vcc.
  • the gate of the transistor T04 and the gate of the transistor T04' are connected with each other to an input terminal to which a second control signal ⁇ 2 is supplied from the clock generator 10.
  • the source and drain of the transistor T02 that are connected commonly with each other as already described are connected to another input terminal to which a third control signal ⁇ 3 is supplied from the clock generator 10.
  • a capacitance provided by a MOS transistor T11 is connected between the gate and the source of the MOS transistor T01'.
  • the circuit of FIG. 2 is driven by a drive voltage that is supplied to the node N01, and for this purpose, a precharge circuit 12 is provided.
  • the precharge circuit is supplied with the supply voltage Vcc and supplies the same to the node N01.
  • the level of the control signals ⁇ 1 and ⁇ 3 are set at zero while the level of the signal ⁇ 2 is set at Vcc at the beginning of operation. See FIG. 3.
  • the supply voltage Vcc appears at the node N01 and the electric charges are accumulated in the capacitance that is provided by the MOS transistor T02. Further, the electric charges are accumulated in the capacitor T01 during this interval.
  • the level of the control signal ⁇ 1 is increased as shown in FIG. 3.
  • the transistor T01 starts to conduct while the transistor T04 starts to cause transition to the unconductive state.
  • the voltage level of the node N01 decreases momentarily until the transistor T04 turns off completely.
  • a word line voltage starts to appear on the main word line 14, as shown in FIG. 3.
  • the control signal ⁇ 3 is activated such that the level of the signal ⁇ 3 increases from zero to the Vcc level.
  • the electric charges that have been accumulated in the capacitor T02 are transferred to the node N01, and the voltage level of the node N01 is boosted as shown in FIG. 3.
  • the word line voltage appearing at the main word line 14 is boosted.
  • the capacitor T02 functions as the boost circuit for boosting the word line, as described previously.
  • the gate voltage of the transistors T01 and T01' is also boosted by the capacitor T11.
  • the increase in the voltage at the node N01 induces a corresponding increase in the source voltage of the transistor T01', and this increase in the source voltage causes a boosting of the gate voltage of the transistors T01 and T01' via the capacitor T11.
  • the conductive state of the transistor T01 is maintained even when the voltage level at the node N01 is boosted.
  • the conventional word line driver 4 uses a clamp circuit 20 in connection with the main word line 14.
  • the memory cell transistors generally have an extremely thin gate oxide film as a result of miniaturization which is degraded quickly when excessive word line voltage is applied repeatedly to the gate.
  • the clamp circuit 20 includes a MOS transistor 22 having its drain and gate connected with each other, and the supply voltage Vcc is supplied to the source of the transistor 22.
  • the transistor 22 conducts when the level of the main word line 14 exceeds a level Vcc +Vth, wherein Vth represents the threshold voltage of the transistor 22.
  • Vth represents the threshold voltage of the transistor 22.
  • Another and more specific object of the present invention is to provide a semiconductor memory device having a boost circuit in a word line driver for boosting a word line voltage, wherein the excessive boosting of the word line voltage is eliminated.
  • Another object of the present invention is to provide a semiconductor memory device having a boost circuit in a word line driver for boosting a word line, with a clamp circuit provided for preventing excessive boosting of the word line voltage, wherein the voltage overshoot in the word line voltage is eliminated.
  • Another object of the present invention is to provide a semiconductor memory device having a boost circuit for boosting a word line and a clamp circuit cooperating with the word line, wherein the clamp circuit is connected to a gate of a MOS transistor that forms a part of a word line driver and activates the word line in cooperation with the boost circuit, such that the clamp circuit clamps the gate voltage of the MOS transistor at a predetermined level even when the boost circuit is activated.
  • the clamp circuit clamps the gate voltage of the MOS transistor at a predetermined level even when the boost circuit is activated.
  • FIG. 1 is a block diagram showing the overall construction of a conventional semiconductor memory device
  • FIG. 2 is a circuit diagram showing a word line driver of the semiconductor memory device of FIG. 1;
  • FIG. 3 is a diagram showing the operation of the circuit of FIG. 2;
  • FIG. 4 is a circuit diagram showing the principle of the present invention.
  • FIG. 5 is a diagram showing the operation of the circuit of FIG. 4;
  • FIG. 6 is a circuit diagram showing a first embodiment of the present invention.
  • FIGS. 7(A)-7(K) are diagrams showing the operation of the circuit of FIG. 6;
  • FIG. 8 is a circuit diagram showing a second embodiment of the present invention.
  • FIG. 9 is a diagram showing the operation of the circuit of FIG. 8.
  • FIG. 10 is a circuit diagram showing a third embodiment of the present invention.
  • FIG. 4 shows the principle of the present invention.
  • the parts that correspond to those described previously are identified with the same reference numerals and the description thereof will be omitted.
  • the word line driver 4 has the construction substantially identical with the conventional word line driver of FIG. 2, including the boost circuit formed of the MOS transistors T02 and T11.
  • the clamp circuit 26 is not connected to the main word line 14 but to the gate of the transistors T01 and T01'. Thereby, the circuit 26 clamps the voltage ⁇ 1 at the gate of the transistors T01 and T01' at a clamping level of V+2Vth when the voltage ⁇ 1 exceeds the foregoing clamping level.
  • the level Vth herein represents the threshold voltage of the transistors T01 and T01'.
  • FIG. 5 shows the operation of the circuit of FIG. 4.
  • the control signal ⁇ 1 rises similar to FIG. 3 to the Vcc level at first, and is boosted further in response to the rising of the control signal ⁇ 3 to the Vcc level.
  • the level of the signal ⁇ 1 is clamped at the level Vcc+2Vth, and a voltage drop of Vth appears across the gate and the drain of the transistor T01.
  • the word line voltage at the main word line 14 is clamped at the level of Vcc+Vth.
  • the capacitance at the gate of the transistors T01 and T01' is substantially smaller than the capacitance associated with the word line 14, and the clamp circuit 26 can effectively remove the electric charges when the word line voltage is excessively boosted.
  • FIG. 6 shows a first embodiment of the present invention.
  • the parts that have been described previously are identified by the same reference numerals and the description will be omitted.
  • the word line driver circuit 4 includes a circuit 24 for producing the control signal ⁇ 1.
  • the circuit 24 includes an n-channel MOS transistor T15 having a source to which an input control signal ⁇ 4 is supplied from the clock generator 10.
  • the transistor T15 has a gate connected to the supply voltage source for receiving the supply voltage Vcc and a drain connected to the gate of a p-channel MOS transistor T13.
  • the MOS transistor T13 in turn is connected in series to a p-channel MOS transistor T12 and an n-channel MOS transistor T14, wherein the drain of the transistor T13 is connected to the drain of the transistor T12, the source of the transistor T13 is connected to the drain of the transistor T14, and the source of the transistor T12 is connected to the power supply terminal Vcc.
  • the source of the transistor T14 is connected to the ground.
  • the gate of the transistor T12 and the gate of the transistor T14 are connected commonly with each other and receives another control signal ⁇ 5 from the clock generator 10 of FIG. 1.
  • the control signal ⁇ 1 is obtained at the source of the transistor T13.
  • the control signal ⁇ 1 is produced by the circuit 24 based upon the control signals ⁇ 4 and ⁇ 5 rather than given directly from the clock generator 10.
  • the clamp circuit 26 includes two MOS transistors TR1 and TR2 connected in series and both having the threshold level of Vth, wherein the gate and drain are connected each other in each of the transistors TR1 and TR2, and the transistor TR1 has its source connected to the power supply terminal Vcc.
  • the gate and drain of the transistor TR2 are connected to the gate of the transistors T01 and T01'.
  • the precharge circuit 12 includes a MOS transistor T05 having its drain connected to the power supply terminal Vcc and the source connected to the node N01. The transistor T05 is supplied with a precharge control signal ⁇ P at the gate and is activated in response thereto.
  • FIGS. 7(A)-7(K) explains the operation of the circuit of FIG. 6.
  • the signal /RAS is set to have the high level state as shown in FIG. 7(A)
  • the precharge control signal ⁇ P is set to have the level Vcc+Vth as shown in FIG. 7(B)
  • the control signal ⁇ 4 is set to have the high level state as shown in FIG. 7(F)
  • the control signal ⁇ 5 is set to have the high level state as shown in FIG. 7(G).
  • the level of the control signal ⁇ 2 is held high as shown in FIG. 7(D) and the level of the control signal ⁇ 3 is held low as shown in FIG. 7(E).
  • the transistor T14 In response to the high level state of the signal ⁇ 5, the transistor T14 is turned on and the transistor T12 is turned off. Thereby, the level of the control signal ⁇ 1 is held low as shown in FIG. 7(C). With the low level state of the signal ⁇ 1, the level at a node N02 corresponding to the drain of the transistor T1' is held low as shown in FIG. 7(I). On the other hand, the level of a node N03 corresponding to the gate of the transistor T13 is held at the high level state as shown in FIG. 7(J), in response to the high level state of the control signal ⁇ 4. In this initial state, the level of the word line 14 is held low as shown in FIG. 7(K).
  • the read (or write) operation is started in response to the transition of the /RAS signal as shown in FIG. 7(A).
  • the control signal ⁇ 5 causes a transition to the low level state as shown in FIG. 7(G), and the transistor T14 changes its state from the conductive state to the unconductive state.
  • the transistor T12 causes a transition to the conductive state.
  • the level of the source of the transistor T13 is increased in response to the high level state of the node N03, and the level of the control signal ⁇ 1 starts to rise as shown in FIG. 7(C) to the level Vcc.
  • This increase in the level of the control signal ⁇ 1 in turn causes a boost of the gate voltage of the transistor T13 due to the capacitance of the transistor T13.
  • control signal ⁇ 4 causes a transition to the low level state as shown in FIG. 7(F), and in response thereto, the voltage level of the node N03 decreases as shown in FIG. 7(J). Thereby, the transistor T13 is turned off and the gate of the transistor T01 becomes floating due to the turning off of both transistors T13 and T14.
  • the level of the control signal ⁇ 3 is changed to the high level state as shown in FIG. 7(E), after a momentary voltage drop c1.
  • This momentary voltage drop is caused by the conduction of the transistor T01 in response to the high level state of the control signal ⁇ 1.
  • a corresponding voltage rise c2 appears at the node N02 in correspondence to the voltage drop c1 as shown in FIG. 7(I).
  • the voltage level at the node N01 is boosted as shown in FIG. 7(H), and in response to this, the level of the node N02 is also boosted as shown in FIG. 7(I).
  • the boost of the node N01 causes a boost of the word line voltage on the word line 14 as shown in FIG. 7(K).
  • the boost of the node N02 in turn causes the boost of the control signal ⁇ 1 at the gate of the transistor T01 as shown in FIG. 7(C).
  • This boost is, however, clamped at the level Vcc+2Vth by the clamp circuit 26, and the boost of the voltage level of the word line 14 is clamped at the level of Vcc+Vth as shown in FIG.
  • the transistors TR1 and TR2 cause a flow of electric charges from the gate of the transistors T01 and T01' to the power supply terminal Vcc whenever the voltage level ⁇ 1 exceeds the level Vcc+2Vth.
  • the precharge control signal ⁇ P is disabled after the boosting of the word line is started.
  • the adverse influence of the large capacitance of the word line 14 on the efficiency of removal of electric charges by the clamp circuit 26 is minimized by connecting the clamp circuit at the gate of the transistors T01 and T01'.
  • This in turn enables use of a transistor of modest capability for flowing the drive current for the transistors TR1 and TR2 of the clamp circuit 26, and one can obtain a quick response of the clamp circuit 26.
  • the problem of voltage overshoot of the word line can be eliminated entirely, and one can extend the lifetime of the semiconductor memory device. This in turn results in the improvement in the reliability of systems that employ the semiconductor memory device.
  • the electric stress applied to the gate oxide film of the transistors T01 and T01' is limited to the level 2Vth, even when the boosting is applied and the gate voltage is increased to the level Vcc+2Vth.
  • the word line voltage of Vcc+Vth is directly applied to the gate oxide of the memory cell transistor as the electric stress.
  • the clamping of the word line voltage at the level Vcc+Vth is essential for the long lifetime of the memory cell transistors, while the boosting of the gate of the transistors T01 and T01' to the level Vcc+2Vth causes little adverse effect on these transistors.
  • the capacitance given by the MOS transistor T11 is provided by the capacitance between the drain and the gate of the MOS transistor T01.
  • FIG. 8 shows a second embodiment of the present invention, wherein a single MOS transistor is used for activating the word line.
  • the circuit 2A includes MOS transistors T23-T25 connected in series between the power supply terminal Vcc and the ground, wherein the transistor T23 is a p-channel MOS transistor and is enabled in response to a control signal ⁇ R that is supplied from the clock generator 10 of FIG. 1.
  • the transistors T24 and T25 are formed of an n-channel MOS transistor and is supplied with a selection signal for selecting the word line WL from the address decoder 3. It should be noted that a number of circuits shown in FIG. 8 are provided in the word line decoder 2 in correspondence to each word line WL.
  • the voltage level at a node N24 is changed, and the voltage change at the node N24 is transferred on the one hand to an n-channel MOS transistor T20 via an inverter INV1 and a transistor T22 that is activated in response to a control signal ⁇ V from the clock generator 10, and on the other hand to another n-channel MOS transistor T21 connected in series to the transistor T20 via a second inverter INV2.
  • the word line voltage produced by the word line driver WDD is supplied, while the source of the transistor T21 is connected to the ground.
  • the word line WL is connected to the source of the transistor T20.
  • the word line driver WDD may have a conventional construction and includes a boost circuit. On the other hand, the word line driver WDD does not include a clamp circuit.
  • the clamp circuit 32 at the gate of the transistor T20.
  • the clamp circuit 32 includes transistors T26 and T27 connected in series between the gate of the transistor T20 and the power supply terminal Vcc, wherein each transistor has its gate connected to its drain.
  • the voltage level of the source of the transistor T20 is boosted in correspondence thereto.
  • the gate voltage of the transistor T20 is boosted to the level Vcc+2Vth because of the effect of the capacitance at the gate of the transistor T20.
  • Vth represents the threshold voltage of the transistor T20.
  • the clamp circuit 32 starts to remove the electric charges on the gate of the transistor T20 to the power supply terminal Vcc, and the gate voltage of the transistor T20 is clamped at the level Vcc+2Vth.
  • the transistors T26 and T27 both have the threshold voltage Vth.
  • the word line voltage at the drain of the word line WL is clamped at the level of Vcc+Vth. In this construction, too, one can eliminate the voltage overshoot of the word line voltage effectively and efficiently, as the clamp circuit is connected to the gate of the transistor T20 rather than the word line itself.
  • FIG. 9 shows the operation of the circuit of FIG. 8.
  • the voltage level of the node N21 connected to the gate of the transistor T20 is increased from the level Vss to the level Vcc.
  • the voltage at the node N22 connected to the gate of the transistor T21 decreases to the level Vss. Thereby, the transistor T20 is turned on while the transistor T21 is turned off, and the selection of the word line WL is achieved.
  • the voltage level at the source of the transistor T20 is raised and the boosting of the word line is started.
  • the voltage level at the node N21 is boosted as already described to the level Vcc+2Vth, where the voltage is clamped by the clamp circuit 32, even when the output of the word line drive WDD has increased beyond the level Vcc +Vth, as illustrated in FIG. 9.
  • the word line voltage on the word line WL is clamped at the level Vcc+Vth as already described.
  • no separate capacitance element such as the transistor T11 of the first embodiment is used for boosting the gate voltage of the transistor T20.
  • the principle of the boosting is substantially the same as in the first embodiment, as the capacitance at the gate of the transistor T20 acts as the capacitance provided by the transistor T11 of the first embodiment.
  • FIG. 10 the parts that correspond to those described previously are designated by the same reference numerals and the description thereof will be omitted.
  • the circuit of FIG. 10 corresponds to the circuit of FIG. 8, except that a MOS transistor T28 connected to form a capacitor is used in the clamp circuit now designated by the numeral 34.
  • a MOS transistor T28 connected to form a capacitor is used in the clamp circuit now designated by the numeral 34.
  • the size such as the thickness and area of the gate oxide film of the MOS transistor T28, one can clamp the voltage level of the node N21 at the level of Vcc+2Vth and the word line voltage at the level of Vcc+Vth.
  • the construction of the clamp circuit 34 is of course applicable to the first embodiment, in place of the clamp circuit 26.
  • the clamping level of the word line is not limited the level of Vcc+Vth described heretofore, but to any higher level such as Vcc+2Vth, Vcc+3Vth, . . . , as long as the memory cell transistor can endure the word line voltage. One can achieve this by simply increasing the number of stages of the transistors in the clamp circuit 26 or clamp circuit 32.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
US07/747,049 1990-08-20 1991-08-19 Semiconductor memory device having a boost circuit Expired - Fee Related US5253204A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CA002075410A CA2075410A1 (en) 1991-08-19 1992-08-06 Removable cushion container flat

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2218731A JPH0812754B2 (ja) 1990-08-20 1990-08-20 昇圧回路
JP2-218731 1990-08-20

Publications (1)

Publication Number Publication Date
US5253204A true US5253204A (en) 1993-10-12

Family

ID=16724554

Family Applications (1)

Application Number Title Priority Date Filing Date
US07/747,049 Expired - Fee Related US5253204A (en) 1990-08-20 1991-08-19 Semiconductor memory device having a boost circuit

Country Status (5)

Country Link
US (1) US5253204A (de)
EP (1) EP0472095B1 (de)
JP (1) JPH0812754B2 (de)
KR (1) KR950014242B1 (de)
DE (1) DE69118049T2 (de)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998014946A1 (en) * 1996-10-01 1998-04-09 Microchip Technology Incorporated Voltage reference generator for eprom memory array
US5831470A (en) * 1995-11-23 1998-11-03 Lg Semicon Co., Ltd High-efficiency charge pumping circuit
US5914908A (en) * 1997-03-14 1999-06-22 Hyundai Electronics America Method of operating a boosted wordline
US6160749A (en) * 1997-03-14 2000-12-12 Hyundai Electronics America Pump control circuit
CN1084051C (zh) * 1995-12-06 2002-05-01 西门子公司 驱动场效应晶体管的方法
US6525972B2 (en) * 2000-07-06 2003-02-25 Nec Corporation Semiconductor memory device with boosting control circuit and control method
KR100432985B1 (ko) * 1996-12-12 2004-07-16 지멘스 악티엔게젤샤프트 상승된출력전압을발생시키기위한회로
DE4439661C5 (de) * 1993-11-09 2007-03-29 Samsung Electronics Co., Ltd., Suwon Wortleitungstreiberschaltkreis für eine Halbleiterspeichereinrichtung
US20100214859A1 (en) * 2009-02-20 2010-08-26 International Business Machines Corporation Implementing Boosted Wordline Voltage in Memories
US20100309450A1 (en) * 2004-12-23 2010-12-09 Carl Zeiss Smt Ag Filter device for the compensation of an asymmetric pupil illumination
US20110158029A1 (en) * 2009-12-25 2011-06-30 Kabushiki Kaisha Toshiba Word line driving circuit and semiconductor storage device
CN103326699A (zh) * 2012-03-22 2013-09-25 富士通半导体股份有限公司 半导体器件
US8729951B1 (en) 2012-11-27 2014-05-20 Freescale Semiconductor, Inc. Voltage ramp-up protection
USRE47743E1 (en) * 2010-01-27 2019-11-26 Novatek Microelectronics Corp. Output buffer circuit and method for avoiding voltage overshoot

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940005509B1 (ko) * 1992-02-14 1994-06-20 삼성전자 주식회사 승압단속회로및이를구비하는출력버퍼회로
DE4324855C1 (de) * 1993-07-23 1994-09-22 Siemens Ag Ladungspumpe
JP2570984B2 (ja) * 1993-10-06 1997-01-16 日本電気株式会社 出力回路
JPH09320267A (ja) * 1996-05-28 1997-12-12 Oki Micro Design Miyazaki:Kk 昇圧回路の駆動方法および昇圧回路
US6134146A (en) * 1998-10-05 2000-10-17 Advanced Micro Devices Wordline driver for flash electrically erasable programmable read-only memory (EEPROM)
US6430087B1 (en) * 2000-02-28 2002-08-06 Advanced Micro Devices, Inc. Trimming method and system for wordline booster to minimize process variation of boosted wordline voltage
US7894230B2 (en) 2009-02-24 2011-02-22 Mosaid Technologies Incorporated Stacked semiconductor devices including a master device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62197997A (ja) * 1986-02-26 1987-09-01 Hitachi Ltd 半導体記憶装置
US4807190A (en) * 1986-03-12 1989-02-21 Hitachi Ltd. Semiconductor integrated circuit device
EP0367450A2 (de) * 1988-10-31 1990-05-09 Texas Instruments Incorporated Verfahren und Ladungsfesthaltesignal-Erhöhungsschaltung
US5051959A (en) * 1985-08-14 1991-09-24 Fujitsu Limited Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5862895A (ja) * 1981-10-12 1983-04-14 Mitsubishi Electric Corp 半導体記憶回路
JPS61294695A (ja) * 1985-06-20 1986-12-25 Mitsubishi Electric Corp 半導体集積回路装置
JPS6243895A (ja) * 1985-08-20 1987-02-25 Nec Corp 半導体メモリ回路
JPS63239673A (ja) * 1987-03-27 1988-10-05 Hitachi Ltd 半導体集積回路装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051959A (en) * 1985-08-14 1991-09-24 Fujitsu Limited Complementary semiconductor memory device including cell access transistor and word line driving transistor having channels of different conductivity type
JPS62197997A (ja) * 1986-02-26 1987-09-01 Hitachi Ltd 半導体記憶装置
US4807190A (en) * 1986-03-12 1989-02-21 Hitachi Ltd. Semiconductor integrated circuit device
EP0367450A2 (de) * 1988-10-31 1990-05-09 Texas Instruments Incorporated Verfahren und Ladungsfesthaltesignal-Erhöhungsschaltung

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
IEEE Journal of Solid State Circuits, vol. 16, No. 5, Oct. 1981 pp. 492 498, Taniguchi et al. Fully Boosted 64K Dynamic Ram with Automatic and Self Refresh . *
IEEE Journal of Solid-State Circuits, vol. 16, No. 5, Oct. 1981 pp. 492-498, Taniguchi et al. "Fully Boosted 64K Dynamic Ram with Automatic and Self Refresh".
Patent Abstracts of Japan, vol. 7, No. 152, Jul. 5, 1983, JP A 58 62895. *
Patent Abstracts of Japan, vol. 7, No. 152, Jul. 5, 1983, JP-A 58-62895.

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4439661C5 (de) * 1993-11-09 2007-03-29 Samsung Electronics Co., Ltd., Suwon Wortleitungstreiberschaltkreis für eine Halbleiterspeichereinrichtung
US5831470A (en) * 1995-11-23 1998-11-03 Lg Semicon Co., Ltd High-efficiency charge pumping circuit
CN1084051C (zh) * 1995-12-06 2002-05-01 西门子公司 驱动场效应晶体管的方法
US5805507A (en) * 1996-10-01 1998-09-08 Microchip Technology Incorporated Voltage reference generator for EPROM memory array
WO1998014946A1 (en) * 1996-10-01 1998-04-09 Microchip Technology Incorporated Voltage reference generator for eprom memory array
KR100432985B1 (ko) * 1996-12-12 2004-07-16 지멘스 악티엔게젤샤프트 상승된출력전압을발생시키기위한회로
US6160749A (en) * 1997-03-14 2000-12-12 Hyundai Electronics America Pump control circuit
US5914908A (en) * 1997-03-14 1999-06-22 Hyundai Electronics America Method of operating a boosted wordline
US6525972B2 (en) * 2000-07-06 2003-02-25 Nec Corporation Semiconductor memory device with boosting control circuit and control method
US20100309450A1 (en) * 2004-12-23 2010-12-09 Carl Zeiss Smt Ag Filter device for the compensation of an asymmetric pupil illumination
US20100214859A1 (en) * 2009-02-20 2010-08-26 International Business Machines Corporation Implementing Boosted Wordline Voltage in Memories
US7924633B2 (en) * 2009-02-20 2011-04-12 International Business Machines Corporation Implementing boosted wordline voltage in memories
US20110158029A1 (en) * 2009-12-25 2011-06-30 Kabushiki Kaisha Toshiba Word line driving circuit and semiconductor storage device
US8270247B2 (en) * 2009-12-25 2012-09-18 Kabushiki Kaisha Toshiba Word line driving circuit and semiconductor storage device
USRE47743E1 (en) * 2010-01-27 2019-11-26 Novatek Microelectronics Corp. Output buffer circuit and method for avoiding voltage overshoot
CN103326699A (zh) * 2012-03-22 2013-09-25 富士通半导体股份有限公司 半导体器件
US20130249605A1 (en) * 2012-03-22 2013-09-26 Fujitsu Semiconductor Limited Semiconductor device
US8836380B2 (en) * 2012-03-22 2014-09-16 Transphorm Japan, Inc. Bootstrap circuit
US8729951B1 (en) 2012-11-27 2014-05-20 Freescale Semiconductor, Inc. Voltage ramp-up protection

Also Published As

Publication number Publication date
DE69118049T2 (de) 1996-08-01
JPH0812754B2 (ja) 1996-02-07
EP0472095A3 (en) 1992-11-19
JPH04102292A (ja) 1992-04-03
DE69118049D1 (de) 1996-04-25
EP0472095A2 (de) 1992-02-26
KR920005151A (ko) 1992-03-28
KR950014242B1 (ko) 1995-11-23
EP0472095B1 (de) 1996-03-20

Similar Documents

Publication Publication Date Title
US5253204A (en) Semiconductor memory device having a boost circuit
EP0713222B1 (de) Integrierte Speicherschaltungsanordnung
US5619162A (en) Dram using word line potential circuit control
US5764562A (en) Semiconductor memory device
US6333874B2 (en) Semiconductor memory device having normal and standby modes, semiconductor integrated circuit and mobile electronic unit
US5047984A (en) Internal synchronous static RAM
EP0389202A2 (de) Dynamischer Direktzugriffsspeicher mit verbesserter Wortleitungssteuerung
US5220527A (en) Dynamic type semiconductor memory device
EP0142376B1 (de) Dynamischer RAM-Speicher
US5650970A (en) semiconductor memory device having a flash write function
US5282171A (en) Semiconductor memory device having a word driver
EP0202025A2 (de) Spannungserhöherschaltung
KR950009074B1 (ko) 다이너믹형 반도체 기억장치
US5327026A (en) Self-timed bootstrap decoder
JP2003016793A (ja) 半導体記憶装置用アドレス回路及びｘデコーダと半導体記憶装置
USRE36159E (en) Semiconductor integrated circuit device having built-in voltage drop circuit
EP0811985A1 (de) Verbesserter halbleiterspeicher mit einem zeilenauswahlsignal ausgebendem zeilendekoders und sein steuerverfahren
JP2511910B2 (ja) 半導体記憶装置
US5777934A (en) Semiconductor memory device with variable plate voltage generator
US6262934B1 (en) Memory circuit including word line reset circuit and method of resetting word line
JP3805987B2 (ja) 半導体記憶装置
KR100200907B1 (ko) 전체 피크치 전류를 낮추어 액세스 타임을 단축하기 위한 판독신호 증폭기 구동회로를 구비한 다이내믹 반도체 기억장치
JP2801654B2 (ja) ダイナミック型半導体記憶装置
US6091290A (en) Semiconductor integrated circuit
JPH04353693A (ja) 半導体記憶装置

Legal Events

Date Code Title Description
AS Assignment

Owner name: FUJITSU LIMITED

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:HATAKEYAMA, ATSUSHI;NAKANO, MASAO;REEL/FRAME:005846/0018

Effective date: 19910805

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20051012