USRE47743E1 - Output buffer circuit and method for avoiding voltage overshoot - Google Patents

Output buffer circuit and method for avoiding voltage overshoot Download PDF

Info

Publication number
USRE47743E1
USRE47743E1 US14/800,712 US201514800712A USRE47743E US RE47743 E1 USRE47743 E1 US RE47743E1 US 201514800712 A US201514800712 A US 201514800712A US RE47743 E USRE47743 E US RE47743E
Authority
US
United States
Prior art keywords
output
circuit
voltage
input
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US14/800,712
Inventor
Xie-Ren Hsu
Ji-Ting Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Novatek Microelectronics Corp
Original Assignee
Novatek Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Novatek Microelectronics Corp filed Critical Novatek Microelectronics Corp
Priority to US14/800,712 priority Critical patent/USRE47743E1/en
Application granted granted Critical
Publication of USRE47743E1 publication Critical patent/USRE47743E1/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018514—Interface arrangements with at least one differential stage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0275—Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/441—Protection of an amplifier being implemented by clamping means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45136—One differential amplifier in IC-block form being shown

Definitions

  • the present invention relates to an output buffer circuit for avoiding voltage overshoot, and more particularly, to an output buffer circuit that prevents leakage currents from changing a systematic offset voltage by timely closing a clamping circuit.
  • An output stage of a present display driver adopts an operational amplifier circuit to rapidly charge and discharge a load end, such that driving capability of the display driver is enhanced.
  • an operational amplifier circuit to rapidly charge and discharge a load end, such that driving capability of the display driver is enhanced.
  • inner currents of the operational amplifier cannot be recovered immediately, the rapid charging or discharging of the load end would a voltage overshoot.
  • a clamping circuit is added between an output terminal of the operational amplifier and an input terminal of the output stage thereof to avoid the voltage overshoot.
  • the clamping circuit may not be completely closed, resulting in certain leakage currents (in approximate nA degree). For low power application, such leakage currents may change a systematic offset voltage of the display driver.
  • FIG. 1 is a schematic diagram of an operational amplifier 10 according to the prior art.
  • the operational amplifier 10 is a two stage amplifier, and includes an input stage 11 , an output bias circuit 12 , an output stage 13 and a clamping circuit 14 .
  • the input stage 11 is a differential input stage having a rail-to-rail input range, and includes a positive input terminal AVP and a negative input terminal AVN.
  • the input stage 11 includes input transistors N1, N2, P1 and P2 coupled to the input terminals AVP and AVN and bias transistors N3 and P3 coupled to the bias terminals VBN1 and VBP1, respectively.
  • the input stage 11 generates a current signal IAB according to an input voltage received by the positive input terminal AVP.
  • the output bias circuit 12 is coupled to the input stage 11 , for generating a dynamic bias VAB between nodes AA and AB (i.e. a voltage difference between the node AA and the node AB) according to the current signal IAB.
  • the output stage 13 is a class AB output stage composed of transistors P 9 and N 9 , and includes an input output terminal AVF reversely coupled to the negative input terminal AVN of the input stage 11 .
  • the output stage 13 provides a driving current to the output terminal AVF according to the dynamic bias VAB, so as to generate an output voltage.
  • the clamping circuit 14 consists of transistors POS 1 , POS 2 , NOS 1 , and NOS 2 , for maintaining the output voltage of the operational amplifier 10 within a predefined range, so as to avoid the voltage overshoot.
  • the output stage 13 increases the driving current for the output terminal AVF to enhance the output voltage of the operational amplifier, as shown by solid lines in FIG. 1 .
  • the output stage 13 reduces the driving current for the output terminal AVF to decrease the output voltage of the operational amplifier, as shown by dot lines in FIG. 1 .
  • a level of the output voltage makes overdrive voltages of the transistors POS 2 or NOS 2 smaller than threshold voltages thereof, i.e. (AVF-VBPOS) ⁇ Vthp or (VBNOS-AVF) ⁇ Vthn, and results in the transistors POS 2 or NOS 2 being closed.
  • the clamping circuit 14 has no effects on the charging and discharging operations of the operational amplifier.
  • the overdrive voltages of the transistors POS 2 or NOS 2 are larger than the threshold voltages thereof, i.e.
  • the transistors POS 2 or NOS 2 may not be completely closed, resulting in a certain leakage currents.
  • the output voltage of the operational amplifier may be as low as 0.1 volt, thereby the transistors NOS 1 and NOS 2 cannot be completely closed, and results in a certain currents flowing through the transistors NOS 1 and NOS 2 (from the output terminal AVF into the node AB).
  • the present invention discloses an output buffer circuit for avoiding voltage overshoot.
  • the output buffer circuit includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit.
  • the input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal.
  • the input stage generates a current signal according to the input voltage.
  • the output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal.
  • the output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.
  • the clamp circuit is coupled to the input stage, the output bias circuit and the output stage, for drawing currents from the output terminal to help the current signal to return the dynamic bias to a proper level when the output voltage exceeds a predefined range.
  • the control unit is coupled to the clamp circuit, for activating the clamp circuit when the output buffer circuit receives the input voltage and for deactivating the clamp circuit when the output voltage reaches a steady state.
  • the present invention further discloses a method of avoiding voltage overshoot for an output buffer circuit.
  • the output buffer circuit includes an input stage, an output stage and a clamp circuit.
  • the input stage generates a current signal according to an input voltage.
  • the output stage generates an output voltage according to the current signal.
  • the clamp circuit is coupled to the input stage and the output stage, for clamping the output voltage within a predefined range.
  • the method includes activating the clamp circuit when the input voltage is received, starting to output the output voltage, and deactivating the clamp circuit when the output voltage reaches a steady state.
  • FIG. 1 is a schematic diagram of an operational amplifier according to the prior art.
  • FIG. 2 is a schematic diagram of an output buffer circuit capable of improving voltage overshoot according to an embodiment of the present invention.
  • FIG. 3 is a timing diagram of signals of the output buffer circuit in FIG. 2 .
  • FIG. 4 is a schematic diagram of the control unit in FIG. 1 according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the control unit in FIG. 1 according to another embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a voltage overshoot elimination process according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of an output buffer circuit 20 capable of improving voltage overshoot according to an embodiment of the present invention.
  • the output buffer circuit 20 includes an input stage 21 , an output bias circuit 22 , an output stage 23 , a clamping circuit 24 and a control unit 25 .
  • the input stage 21 is a differential input stage having a rail-to-rail input range, and includes a positive input terminal AVP and a negative input terminal AVN.
  • the structure of the input stage 21 is similar to the structure of the input stage 11, so the elements and signals having similar functions are denoted by the same symbols.
  • the input stage 11 21 generates a current signal IAB according to an input voltage received by the positive input terminal AVP.
  • the output bias circuit 22 is coupled to the input stage 21 , for generating a dynamic bias VAB between nodes AA and AB (i.e. a voltage difference between the node AA and the node AB) according to the current signal IAB.
  • the output stage 23 is a class AB output stage composed of transistors P 9 and N 9 , and includes an input terminal AVF reversely coupled to the negative input terminal AVN of the input stage 21 .
  • the output stage 23 provides a driving current to the output terminal AVF according to the dynamic bias VAB, so as to generate an output voltage.
  • the clamping circuit 24 consists of transistors POS 1 , POS 2 , NOS 1 , and NOS 2 , for drawing currents from the output terminal AVF to help the current signal IAB for returning the dynamic bias to a predefined level when the output voltage exceeds a predefined range, so as to avoid the voltage overshoot.
  • the control unit 25 is coupled to the clamp circuit 24 , for activating the clamp circuit 24 when the output buffer circuit 20 receives the input voltage and for deactivating the clamp circuit 24 when the output voltage reaches a steady state.
  • the input stage 21 , the output bias circuit 22 , the output stage 23 and the clamping circuit 24 are merely an exemplary embodiment of the present invention, which can be implemented by any kind of operational amplifier circuit, and is not limited to this.
  • the transistors POS 1 and POS 2 are P-type metal-oxide-semiconductor field-effect (MOSFET) transistors, for clamping the output voltage under a predefined high voltage level; while the transistors NOS 1 and NOS 2 are N-type MOSFETs, for clamping the output voltage over a predefined low voltage level.
  • MOSFET metal-oxide-semiconductor field-effect
  • a gate of the transistor POS 2 is coupled to an operating bias VBPOS
  • a gate of the transistor NOS 2 is coupled to an operating bias VBNOS.
  • the operating biases VBPOS and VBNOS are switched by the control unit 25 .
  • the control unit 25 switches the operating biases VBPOS and VBNOS to a normal bias level to activate the clamping circuit 24 ; whereas, when a voltage level of the output terminal AVF reaches a steady state, the control unit 25 switches the operating biases VBPOS and VBNOS to a power supply voltage VDDA and a ground voltage GNDA, respectively. Such that the transistors POS 2 and NOS 2 are closed, so as to deactivate the clamping circuit 24 .
  • FIG. 3 is a timing diagram of signals of the output buffer circuit 20 in FIG. 2 .
  • the output buffer circuit 20 receives an analog voltage outputted from a pre-stage circuit. Meanwhile, the operating biases VBPOS and VBNOS are switched to the normal bias level, respectively. Such that the clamping circuit 24 is activated to prevent the voltage level of the output terminal AVF from the voltage overshoot.
  • the control unit 25 switches the operating biases VBPOS and VBNOS to the power supply voltage VDDA and the ground voltage GNDA, respectively.
  • the embodiment of the present invention can prevent the leakage currents of the clamping circuit 24 from attacking the bias status of the output stage and the gain of the whole operational amplifier.
  • the control unit 25 can determine whether the output voltage reaches the steady state by following two methods, and is not limited to these.
  • One method is determining the output voltage reaches the steady state when the output buffer circuit 20 receives the output input voltage for a predefined time; while the other method is determining whether the output voltage reaches the steady state by detecting voltage difference between the output terminal AVF and the positive input terminal AVP after the output buffer circuit 20 receives the input voltage.
  • FIG. 4 is a schematic diagram of the control unit 25 in FIG. 1 according to an embodiment of the present invention.
  • the input stage 21 , the output bias circuit 22 , the output stage 23 and the clamping circuit 24 in FIG. 1 are represented by an operational amplifier 41 .
  • the control unit 25 includes a trigger circuit 252 and a timer 254 .
  • the trigger circuit 252 is used for generating a trigger signal T 1 when the output buffer circuit 20 receives the input voltage, such as entering the data load phase.
  • the timer 254 is coupled to the trigger circuit 252 , for calculating the predefined time according to the trigger signal T 1 , so as to provide a basis for the control unit 25 to determine whether the output voltage reaches the steady state. As a result, after the predetermined time, the control unit 25 is able to switch the operating biases VBPOS and VBNOS to the power supply voltage VDDA and the ground voltage GNDA, respectively, so as to deactivate the clamping circuit 24 .
  • FIG. 5 is a schematic diagram of the control unit 25 in FIG. 1 according to another embodiment of the present invention.
  • the input stage 21 , the output bias circuit 22 , the output stage 23 and the clamping circuit 24 in FIG. 1 are represented by an operational amplifier 51 .
  • the control unit 25 includes a voltage detection circuit 256 and a comparison unit 258 .
  • the voltage detection circuit 256 is coupled to the positive input terminal AVP and the output terminal AVF, for detecting voltage levels of the positive input terminal AVP and the output terminal AVF.
  • the comparison unit 258 is coupled to the voltage detection circuit 256 , for determining that the output voltage reaches the steady state when the voltage difference between the output terminal AVF and the positive input terminal AVP is smaller than a predefined value. Therefore, when the output voltage reaches the steady state, the control unit 25 is able to switch the operating biases VBPOS and VBNOS to the power supply voltage VDDA and the ground voltage GNDA, respectively, so as to deactivate the clamping circuit 24 .
  • the present invention is able to solve a problem that the clamping circuit cannot be completely closed and therefore influences the systematic offset voltage of the operational amplifier. Additionally, circuit characteristics become more stable without extra current consumption and area cost for the operational amplifier.
  • FIG. 6 is a schematic diagram of a voltage overshoot elimination process 60 according to an embodiment of the present invention.
  • the voltage overshoot elimination process 60 is an operating process of the above output buffer circuit 20 , and includes the following steps:
  • Step 600 Start.
  • Step 610 Activate the clamp circuit 24 when the input voltage is received.
  • Step 620 Start to output the output voltage.
  • Step 630 Deactivate the clamp circuit 24 when the output voltage reaches the steady state.
  • Step 640 End.
  • the output buffer circuit 20 activates the clamp circuit 24 when receiving the input voltage.
  • the output buffer circuit 20 starts to output the output voltage. Not until the output voltage reaches the steady state, does the output buffer circuit 20 deactivates the clamping circuit 24 .
  • Operations of the output buffer circuit are detailed in the above embodiments, and are not narrated herein.
  • the present invention eliminates the voltage overshoot caused by the strong driving capability of the output stage and avoids the systematic offset voltage being influenced in the low power application via the timing control. In addition, the current consumption and area cost of the operational amplifier are not increased.

Abstract

An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer circuit for avoiding voltage overshoot, and more particularly, to an output buffer circuit that prevents leakage currents from changing a systematic offset voltage by timely closing a clamping circuit.
2. Description of the Prior Art
An output stage of a present display driver adopts an operational amplifier circuit to rapidly charge and discharge a load end, such that driving capability of the display driver is enhanced. However, if inner currents of the operational amplifier cannot be recovered immediately, the rapid charging or discharging of the load end would a voltage overshoot. In general, a clamping circuit is added between an output terminal of the operational amplifier and an input terminal of the output stage thereof to avoid the voltage overshoot. However, under a situation that the operational amplifier has full swing output, the clamping circuit may not be completely closed, resulting in certain leakage currents (in approximate nA degree). For low power application, such leakage currents may change a systematic offset voltage of the display driver.
Please refer to FIG. 1. FIG. 1 is a schematic diagram of an operational amplifier 10 according to the prior art. The operational amplifier 10 is a two stage amplifier, and includes an input stage 11, an output bias circuit 12, an output stage 13 and a clamping circuit 14. The input stage 11 is a differential input stage having a rail-to-rail input range, and includes a positive input terminal AVP and a negative input terminal AVN. The input stage 11 includes input transistors N1, N2, P1 and P2 coupled to the input terminals AVP and AVN and bias transistors N3 and P3 coupled to the bias terminals VBN1 and VBP1, respectively. The input stage 11 generates a current signal IAB according to an input voltage received by the positive input terminal AVP. The output bias circuit 12 is coupled to the input stage 11, for generating a dynamic bias VAB between nodes AA and AB (i.e. a voltage difference between the node AA and the node AB) according to the current signal IAB. The output stage 13 is a class AB output stage composed of transistors P9 and N9, and includes an input output terminal AVF reversely coupled to the negative input terminal AVN of the input stage 11. The output stage 13 provides a driving current to the output terminal AVF according to the dynamic bias VAB, so as to generate an output voltage. The clamping circuit 14 consists of transistors POS1, POS2, NOS1, and NOS2, for maintaining the output voltage of the operational amplifier 10 within a predefined range, so as to avoid the voltage overshoot.
When the operational amplifier 10 charges the load, such as receiving a high level input voltage, a voltage of the positive input terminal AVP increases, such that the current signal IAB flowing through the output bias circuit 12 decreases, and results in decrease of voltages of the nodes AA and AB. Under such circumstances, the output stage 13 increases the driving current for the output terminal AVF to enhance the output voltage of the operational amplifier, as shown by solid lines in FIG. 1. On the contrary, when the operational amplifier 10 discharges the load, such as receiving a low level input voltage, the voltage of the positive input terminal AVP decreases, such that the current signal IAB flowing through the output bias circuit 12 increases, and results in increase of the voltages of the nodes AA and AB. Under such circumstances, the output stage 13 reduces the driving current for the output terminal AVF to decrease the output voltage of the operational amplifier, as shown by dot lines in FIG. 1.
Under normal conditions, a level of the output voltage makes overdrive voltages of the transistors POS2 or NOS2 smaller than threshold voltages thereof, i.e. (AVF-VBPOS)<Vthp or (VBNOS-AVF)<Vthn, and results in the transistors POS2 or NOS2 being closed. Hence, the clamping circuit 14 has no effects on the charging and discharging operations of the operational amplifier. Whereas, when the level of the output voltage exceeds a predefined range, the overdrive voltages of the transistors POS2 or NOS2 are larger than the threshold voltages thereof, i.e. (AVF-VBPOS)>Vthp or (VBNOS-AVF)>Vthn, which results in the transistors POS2 or NOS2 being on. In this case, currents flowing from the output terminal AVF into the nodes AA or AB help the voltages of the nodes AA or AB to return to a normal level, so as to alleviate the voltage overshoot.
However, incases that the operational amplifier has full swing output, the transistors POS2 or NOS2 may not be completely closed, resulting in a certain leakage currents. Take the discharging operation as an example, the output voltage of the operational amplifier may be as low as 0.1 volt, thereby the transistors NOS1 and NOS2 cannot be completely closed, and results in a certain currents flowing through the transistors NOS1 and NOS2 (from the output terminal AVF into the node AB). For the low power application, currents of each path in the operational amplifier become lower and lower, thereby it becomes obvious that variations of currents flowing through the transistors P11 and N11 and a variation of the overdrive voltage caused by the leakage currents, so as to influence a bias status and a static current of the output stage 13. With a change to the static current of the output stage 13, a transconductance of the output stage 13 and a gain of the operational amplifier would also vary. The gain of the operational amplifier directly influences a systematic offset voltage of the operational amplifier.
In brief, for the low power application, the current of each path of the operational amplifier becomes lower with time. In the full swing output case, the clamping circuit cannot be completely closed, resulting in a more obvious change to the static current of the output bias circuit. Accordingly, the gain of the whole operational amplifier changes, so as to influence the systematic offset voltage of the operational amplifier.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the claimed invention to provide an output buffer circuit and method for avoiding voltage overshoot.
The present invention discloses an output buffer circuit for avoiding voltage overshoot. The output buffer circuit includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage. The clamp circuit is coupled to the input stage, the output bias circuit and the output stage, for drawing currents from the output terminal to help the current signal to return the dynamic bias to a proper level when the output voltage exceeds a predefined range. The control unit is coupled to the clamp circuit, for activating the clamp circuit when the output buffer circuit receives the input voltage and for deactivating the clamp circuit when the output voltage reaches a steady state.
The present invention further discloses a method of avoiding voltage overshoot for an output buffer circuit. The output buffer circuit includes an input stage, an output stage and a clamp circuit. The input stage generates a current signal according to an input voltage. The output stage generates an output voltage according to the current signal. The clamp circuit is coupled to the input stage and the output stage, for clamping the output voltage within a predefined range. The method includes activating the clamp circuit when the input voltage is received, starting to output the output voltage, and deactivating the clamp circuit when the output voltage reaches a steady state.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of an operational amplifier according to the prior art.
FIG. 2 is a schematic diagram of an output buffer circuit capable of improving voltage overshoot according to an embodiment of the present invention.
FIG. 3 is a timing diagram of signals of the output buffer circuit in FIG. 2.
FIG. 4 is a schematic diagram of the control unit in FIG. 1 according to an embodiment of the present invention.
FIG. 5 is a schematic diagram of the control unit in FIG. 1 according to another embodiment of the present invention.
FIG. 6 is a schematic diagram of a voltage overshoot elimination process according to an embodiment of the present invention.
 DETAILED DESCRIPTION
Please refer to FIG. 2. FIG. 2 is a schematic diagram of an output buffer circuit 20 capable of improving voltage overshoot according to an embodiment of the present invention. The output buffer circuit 20 includes an input stage 21, an output bias circuit 22, an output stage 23, a clamping circuit 24 and a control unit 25. The input stage 21 is a differential input stage having a rail-to-rail input range, and includes a positive input terminal AVP and a negative input terminal AVN. The structure of the input stage 21 is similar to the structure of the input stage 11, so the elements and signals having similar functions are denoted by the same symbols. The input stage 11 21 generates a current signal IAB according to an input voltage received by the positive input terminal AVP. The output bias circuit 22 is coupled to the input stage 21, for generating a dynamic bias VAB between nodes AA and AB (i.e. a voltage difference between the node AA and the node AB) according to the current signal IAB. The output stage 23 is a class AB output stage composed of transistors P9 and N9, and includes an input terminal AVF reversely coupled to the negative input terminal AVN of the input stage 21. The output stage 23 provides a driving current to the output terminal AVF according to the dynamic bias VAB, so as to generate an output voltage. The clamping circuit 24 consists of transistors POS1, POS2, NOS1, and NOS2, for drawing currents from the output terminal AVF to help the current signal IAB for returning the dynamic bias to a predefined level when the output voltage exceeds a predefined range, so as to avoid the voltage overshoot. The control unit 25 is coupled to the clamp circuit 24, for activating the clamp circuit 24 when the output buffer circuit 20 receives the input voltage and for deactivating the clamp circuit 24 when the output voltage reaches a steady state. Please note that the input stage 21, the output bias circuit 22, the output stage 23 and the clamping circuit 24 are merely an exemplary embodiment of the present invention, which can be implemented by any kind of operational amplifier circuit, and is not limited to this.
In the embodiment of the present invention, the transistors POS1 and POS2 are P-type metal-oxide-semiconductor field-effect (MOSFET) transistors, for clamping the output voltage under a predefined high voltage level; while the transistors NOS1 and NOS2 are N-type MOSFETs, for clamping the output voltage over a predefined low voltage level. A gate of the transistor POS2 is coupled to an operating bias VBPOS, while a gate of the transistor NOS2 is coupled to an operating bias VBNOS. The operating biases VBPOS and VBNOS are switched by the control unit 25. When the output buffer circuit 20 receives the input voltage, the control unit 25 switches the operating biases VBPOS and VBNOS to a normal bias level to activate the clamping circuit 24; whereas, when a voltage level of the output terminal AVF reaches a steady state, the control unit 25 switches the operating biases VBPOS and VBNOS to a power supply voltage VDDA and a ground voltage GNDA, respectively. Such that the transistors POS2 and NOS2 are closed, so as to deactivate the clamping circuit 24.
Please refer to FIG. 3. FIG. 3 is a timing diagram of signals of the output buffer circuit 20 in FIG. 2. First, in a data loading phase, the output buffer circuit 20 receives an analog voltage outputted from a pre-stage circuit. Meanwhile, the operating biases VBPOS and VBNOS are switched to the normal bias level, respectively. Such that the clamping circuit 24 is activated to prevent the voltage level of the output terminal AVF from the voltage overshoot. Next, when the voltage level of the output terminal AVF reaches the steady state, the control unit 25 switches the operating biases VBPOS and VBNOS to the power supply voltage VDDA and the ground voltage GNDA, respectively. Such that the transistors POS2 and NOS2 are closed compulsorily, so as to eliminate currents flowing through the transistors POS1, POS2, NOS1, and NOS2. As a result, when the output voltage reaches the steady state, the embodiment of the present invention can prevent the leakage currents of the clamping circuit 24 from attacking the bias status of the output stage and the gain of the whole operational amplifier.
In the embodiment of the present invention, the control unit 25 can determine whether the output voltage reaches the steady state by following two methods, and is not limited to these. One method is determining the output voltage reaches the steady state when the output buffer circuit 20 receives the output input voltage for a predefined time; while the other method is determining whether the output voltage reaches the steady state by detecting voltage difference between the output terminal AVF and the positive input terminal AVP after the output buffer circuit 20 receives the input voltage.
For example, please refer to FIG. 4. FIG. 4 is a schematic diagram of the control unit 25 in FIG. 1 according to an embodiment of the present invention. For clarity, the input stage 21, the output bias circuit 22, the output stage 23 and the clamping circuit 24 in FIG. 1 are represented by an operational amplifier 41. As shown in FIG. 4, the control unit 25 includes a trigger circuit 252 and a timer 254. The trigger circuit 252 is used for generating a trigger signal T1 when the output buffer circuit 20 receives the input voltage, such as entering the data load phase. The timer 254 is coupled to the trigger circuit 252, for calculating the predefined time according to the trigger signal T1, so as to provide a basis for the control unit 25 to determine whether the output voltage reaches the steady state. As a result, after the predetermined time, the control unit 25 is able to switch the operating biases VBPOS and VBNOS to the power supply voltage VDDA and the ground voltage GNDA, respectively, so as to deactivate the clamping circuit 24.
Please refer to FIG. 5. FIG. 5 is a schematic diagram of the control unit 25 in FIG. 1 according to another embodiment of the present invention. Similarly, the input stage 21, the output bias circuit 22, the output stage 23 and the clamping circuit 24 in FIG. 1 are represented by an operational amplifier 51. As shown in FIG. 5, the control unit 25 includes a voltage detection circuit 256 and a comparison unit 258. The voltage detection circuit 256 is coupled to the positive input terminal AVP and the output terminal AVF, for detecting voltage levels of the positive input terminal AVP and the output terminal AVF. The comparison unit 258 is coupled to the voltage detection circuit 256, for determining that the output voltage reaches the steady state when the voltage difference between the output terminal AVF and the positive input terminal AVP is smaller than a predefined value. Therefore, when the output voltage reaches the steady state, the control unit 25 is able to switch the operating biases VBPOS and VBNOS to the power supply voltage VDDA and the ground voltage GNDA, respectively, so as to deactivate the clamping circuit 24.
Through the above embodiments, the present invention is able to solve a problem that the clamping circuit cannot be completely closed and therefore influences the systematic offset voltage of the operational amplifier. Additionally, circuit characteristics become more stable without extra current consumption and area cost for the operational amplifier.
Please refer to FIG. 6. FIG. 6 is a schematic diagram of a voltage overshoot elimination process 60 according to an embodiment of the present invention. The voltage overshoot elimination process 60 is an operating process of the above output buffer circuit 20, and includes the following steps:
Step 600: Start.
Step 610: Activate the clamp circuit 24 when the input voltage is received.
Step 620: Start to output the output voltage.
Step 630: Deactivate the clamp circuit 24 when the output voltage reaches the steady state.
Step 640: End.
According to the voltage overshoot elimination process 60, the output buffer circuit 20 activates the clamp circuit 24 when receiving the input voltage. Next, the output buffer circuit 20 starts to output the output voltage. Not until the output voltage reaches the steady state, does the output buffer circuit 20 deactivates the clamping circuit 24. Operations of the output buffer circuit are detailed in the above embodiments, and are not narrated herein.
To sum up, by adding the clamping circuit to the output buffer circuit, the present invention eliminates the voltage overshoot caused by the strong driving capability of the output stage and avoids the systematic offset voltage being influenced in the low power application via the timing control. In addition, the current consumption and area cost of the operational amplifier are not increased.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.

Claims (24)

What is claimed is:
1. An output buffer circuit for avoiding voltage overshoot, the output buffer circuit comprising:
an input stage circuit comprising a positive input terminal, for receiving an input voltage, and a negative input terminal, — the input stage circuit generating a current signal according to the input voltage;
an output bias circuit, coupled to the input stage circuit, for generating a dynamic bias according to the current signal;
an output stage circuit, coupled to the input stage circuit and the output bias circuit, comprising:
an output terminal, reversely coupled to the negative input terminal; and
at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage;
a clamp circuit, coupled to the input stage circuit, the output bias circuit and the output stage circuit, for drawing currents from the output terminal to help the current signal to return the dynamic bias to a proper level when the output voltage exceeds a predefined range; and
a control unit controller, coupled to the clamp circuit, for activating the clamp circuit when the output buffer circuit receives the input voltage and for deactivating the clamp circuit to prevent a leakage current resulted by flowing through the clamp circuit when the output voltage reaches a steady state.
2. The output buffer circuit of claim 1, wherein the control unit controller determines the output voltage reaches the steady state when the output buffer circuit receives the input voltage for a predefined time.
3. The output buffer circuit of claim 2, wherein the control unit controller comprises:
a trigger circuit, for generating a trigger signal when the output buffer circuit receives the input voltage; and
a timer, coupled to the trigger circuit, for calculating the predefined time according to the trigger signal controlling the controller to switch a voltage for the clamp circuit to deactivate the clamp circuit after the timer receives the trigger signal and then counts the predefined time.
4. The output buffer circuit of claim 1, wherein the control unit controller determines whether the output voltage reaches the steady state by detecting voltage difference between the output terminal and the positive input terminal after the output buffer circuit receives the input voltage.
5. The output buffer circuit of claim 4, wherein the control unit controller comprises:
a voltage detection circuit, coupled to the positive input terminal and the output terminal, for detecting voltage levels of the positive input terminal and the output terminal; and
a comparison unit comparator, coupled to the voltage detection circuit, for determining the output voltage reaches the steady state when the voltage difference between the output terminal and the positive input terminal is smaller than a predefined value.
6. The output buffer circuit of claim 1, wherein the clamp circuit comprises:
a first metal-oxide-semiconductor field-effect transistor (MOSFET), comprising a source first terminal coupled to the output terminal, a gate second terminal coupled to an operating bias, and a drain third terminal; and
a second metal-oxide-semiconductor field-effect transistor (MOSFET), comprising a source first terminal coupled to the drain third terminal of the first MOSFET, a gate second terminal coupled to the output bias circuit and the at least one output transistor, and a drain third terminal coupled to the gate second terminal of the second MOSFET;
wherein a level of the operating bias is switched by the control unit controller.
7. The output buffer circuit of claim 6, wherein the control unit controller switches the operating bias to a first level to activate the clamp circuit when the output buffer circuit receives the input voltage, and switches the operating bias to a second level to deactivate the clamp circuit when the output voltage reaches the steady state.
8. The output buffer circuit of claim 7, wherein the first MOSFET and the second MOSFET are both P type MOSFETs, for clamping the output voltage under a predefined high voltage level, and the second level is a power supply voltage.
9. The output buffer circuit of claim 7, wherein the first MOSFET and the second MOSFET are both N type MOSFETs, for clamping the output voltage over a predefined low voltage level, and the second level is a ground voltage.
10. The output buffer circuit of claim 1, wherein the input stage circuit is a differential input stage circuit having a rail-to-rail input range.
11. The output buffer circuit of claim 10, wherein the input stage circuit comprises an N type metal-oxide-semiconductor (NMOS) differential input pair and a P type metal-oxide-semiconductor (PMOS) differential input pair.
12. The output buffer circuit of claim 1, wherein the output bias circuit comprises a pair of head-to-tail connected complementary metal-oxide-semiconductor (CMOS) transistors.
13. The output buffer circuit of claim 1, wherein the at least one output transistor form a class AB output stage circuit.
14. A method of avoiding voltage overshoot for an output buffer circuit, the output buffer circuit comprising an input stage circuit, an output stage circuit and a clamp circuit, the input stage circuit generating a current signal according to an input voltage, the output stage circuit generating an output voltage according to the current signal, the clamp circuit, coupled to the input stage circuit and the output stage circuit, for clamping the output voltage within a predefined range, the method comprising:
activating the clamp circuit when the input voltage is received;
starting to output the output voltage; and
deactivating the clamp circuit to prevent a leakage current resulted by flowing through the clamp circuit when the output voltage reaches a steady state.
15. The method of claim 14, wherein the step of deactivating the clamp circuit when the output voltage reaches the steady state comprises:
determining the output voltage reaches the steady state when the input voltage is received for a predefined time.
16. The method of claim 14, wherein the step of deactivating the clamp circuit when the output voltage reaches the steady state comprises:
determining whether the output voltage reaches the steady state by detecting voltage difference between the output voltage and the input voltage after the input voltage is received.
17. The method of claim 16, wherein the step of determining whether the output voltage reaches the steady state comprises:
determining the output voltage reaches the steady state when the voltage difference between the output voltage and the input voltage is smaller than a predefined value.
18. An output buffer circuit for avoiding voltage overshoot, comprising:
an input circuit, configured to generate a current signal according to an input voltage;
an output circuit, coupled to the input circuit and configured to generate an output voltage according to the current signal;
a clamp circuit, coupled to the input circuit and the output circuit, and configured to clamp the output voltage within a predefined range; and
a controller, configured to activate the clamp circuit when the input voltage is received and deactivate the clamp circuit to prevent a leakage current flowing through the clamp circuit when the output voltage reaches a steady state.
19. The output buffer circuit of claim 18, wherein the controller determines the output voltage reaches the steady state when the output buffer circuit receives the input voltage for a predefined time.
20. The output buffer circuit of claim 19, wherein the controller comprises:
a trigger circuit, for generating a trigger signal when the output buffer circuit receives the input voltage; and
a timer, coupled to the trigger circuit, for controlling the controller to switch a voltage for the clamp circuit to deactivate the clamp circuit after the timer receives the trigger signal and then counts the predefined time.
21. The output buffer circuit of claim 18, wherein the controller determines whether the output voltage reaches the steady state by detecting voltage difference between the output voltage and the input voltage after the output buffer circuit receives the input voltage.
22. The output buffer circuit of claim 21, wherein the controller comprises:
a voltage detection circuit, coupled to the input circuit and the output circuit, for detecting voltage levels of the input voltage and the output voltage; and
a comparator, coupled to the voltage detection circuit, for determining the output voltage reaches the steady state when the voltage difference between the output voltage and the input voltage is smaller than a predefined value.
23. The output buffer circuit of claim 18, wherein the input circuit is a differential input circuit having a rail-to-rail input range.
24. The output buffer circuit of claim 18, further comprises
an output bias circuit coupled to the input circuit and the output circuit, for generating a dynamic bias according to the current signal.
US14/800,712 2010-01-27 2015-07-16 Output buffer circuit and method for avoiding voltage overshoot Active 2031-02-28 USRE47743E1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/800,712 USRE47743E1 (en) 2010-01-27 2015-07-16 Output buffer circuit and method for avoiding voltage overshoot

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW99102238A 2010-01-27
TW099102238A TWI407694B (en) 2010-01-27 2010-01-27 Output buffer circuit and method for avoiding voltage overshoot
US12/750,671 US8487687B2 (en) 2010-01-27 2010-03-30 Output buffer circuit and method for avoiding voltage overshoot
US14/800,712 USRE47743E1 (en) 2010-01-27 2015-07-16 Output buffer circuit and method for avoiding voltage overshoot

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US12/750,671 Reissue US8487687B2 (en) 2010-01-27 2010-03-30 Output buffer circuit and method for avoiding voltage overshoot

Publications (1)

Publication Number Publication Date
USRE47743E1 true USRE47743E1 (en) 2019-11-26

Family

ID=44308503

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/750,671 Ceased US8487687B2 (en) 2010-01-27 2010-03-30 Output buffer circuit and method for avoiding voltage overshoot
US14/800,712 Active 2031-02-28 USRE47743E1 (en) 2010-01-27 2015-07-16 Output buffer circuit and method for avoiding voltage overshoot

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US12/750,671 Ceased US8487687B2 (en) 2010-01-27 2010-03-30 Output buffer circuit and method for avoiding voltage overshoot

Country Status (2)

Country Link
US (2) US8487687B2 (en)
TW (1) TWI407694B (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102571060B (en) * 2010-12-31 2015-08-12 意法半导体研发（上海）有限公司 High frequency intelligent buffer
JP6027806B2 (en) * 2012-07-25 2016-11-16 ラピスセミコンダクタ株式会社 Output buffer and semiconductor device
US8729951B1 (en) 2012-11-27 2014-05-20 Freescale Semiconductor, Inc. Voltage ramp-up protection
CN103076537B (en) * 2012-12-25 2015-01-14 清华大学 Method for judging power transmission network transient voltage stability based on area rule
JP2015015643A (en) * 2013-07-05 2015-01-22 ローム株式会社 Signal transmission circuit
TWI505059B (en) * 2014-03-21 2015-10-21 Himax Tech Ltd Voltage buffer
TWI608348B (en) * 2015-11-20 2017-12-11 Detection circuit
US9973180B2 (en) 2015-12-30 2018-05-15 Industrial Technology Research Institute Output stage circuit
KR102644012B1 (en) * 2016-11-24 2024-03-08 에스케이하이닉스 주식회사 Amplifier With Output Range Control Function, and Multi-Stage Amplifier Using That
TWI758925B (en) * 2020-10-22 2022-03-21 天鈺科技股份有限公司 Amplifying circuit

Citations (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4378506A (en) * 1979-08-27 1983-03-29 Fujitsu Limited MIS Device including a substrate bias generating circuit
US4920280A (en) * 1987-04-30 1990-04-24 Samsung Electronics Co., Ltd. Back bias generator
US5253204A (en) * 1990-08-20 1993-10-12 Hatakeyama Et Al. Semiconductor memory device having a boost circuit
US5293081A (en) * 1991-05-06 1994-03-08 Motorola, Inc. Driver circuit for output buffers
US5545934A (en) * 1994-12-22 1996-08-13 Alliance Semiconductor Corporation Voltage clamp circuit
US5894238A (en) * 1997-01-28 1999-04-13 Chien; Pien Output buffer with static and transient pull-up and pull-down drivers
US6300834B1 (en) * 2000-12-12 2001-10-09 Elantec Semiconductor, Inc. High performance intermediate stage circuit for a rail-to-rail input/output CMOS operational amplifier
US20020024873A1 (en) * 1994-05-11 2002-02-28 Shigeki Tomishima Dynamic semiconductor memory device having excellent charge retention characteristics
US20050013084A1 (en) * 2003-07-14 2005-01-20 Robert Weger Means for controlling a coil arrangement with electrically variable inductance
US20050068794A1 (en) * 2003-09-26 2005-03-31 Hsiang-Chung Weng Active clamping circuit and power supply system using the same
US20050146313A1 (en) * 2003-05-23 2005-07-07 Linear Technology Corporation Voltage overshoot reduction circuits
US20060170498A1 (en) * 2004-12-31 2006-08-03 Lionel Portmann Class AB operational buffer
US20060192587A1 (en) * 2005-02-25 2006-08-31 Dipankar Bhattacharya Self-bypassing voltage level translator circuit
TW200701641A (en) 2005-06-20 2007-01-01 Faraday Tech Corp Pre-buffer level shifter and output buffer apparatus
US20070018623A1 (en) * 2005-07-21 2007-01-25 Agere Systems Inc. Low-dropout regulator with startup overshoot control
US20070159250A1 (en) * 2006-01-06 2007-07-12 Nec Electronics Corporation Differential amplifier, data driver and display device
US20080252375A1 (en) * 2007-04-10 2008-10-16 Raydium Semiconductor Corporation Voltage-clamping device and operational amplifier and design method thereof
US20090278602A1 (en) * 2008-05-09 2009-11-12 Broadcom Corporation Closed loop surge protection technique for differential amplifiers
US20090310385A1 (en) * 2008-06-13 2009-12-17 Dragan Maksimovic Method, apparatus & system for extended switched-mode controller
US8686708B2 (en) * 2009-03-19 2014-04-01 Kabushiki Kaisha Toshiba Switching circuit

Patent Citations (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4378506A (en) * 1979-08-27 1983-03-29 Fujitsu Limited MIS Device including a substrate bias generating circuit
US4920280A (en) * 1987-04-30 1990-04-24 Samsung Electronics Co., Ltd. Back bias generator
US5253204A (en) * 1990-08-20 1993-10-12 Hatakeyama Et Al. Semiconductor memory device having a boost circuit
US5293081A (en) * 1991-05-06 1994-03-08 Motorola, Inc. Driver circuit for output buffers
US20020024873A1 (en) * 1994-05-11 2002-02-28 Shigeki Tomishima Dynamic semiconductor memory device having excellent charge retention characteristics
US5545934A (en) * 1994-12-22 1996-08-13 Alliance Semiconductor Corporation Voltage clamp circuit
US5894238A (en) * 1997-01-28 1999-04-13 Chien; Pien Output buffer with static and transient pull-up and pull-down drivers
US6300834B1 (en) * 2000-12-12 2001-10-09 Elantec Semiconductor, Inc. High performance intermediate stage circuit for a rail-to-rail input/output CMOS operational amplifier
US20050146313A1 (en) * 2003-05-23 2005-07-07 Linear Technology Corporation Voltage overshoot reduction circuits
US20050013084A1 (en) * 2003-07-14 2005-01-20 Robert Weger Means for controlling a coil arrangement with electrically variable inductance
US20050068794A1 (en) * 2003-09-26 2005-03-31 Hsiang-Chung Weng Active clamping circuit and power supply system using the same
US7358812B2 (en) 2004-12-31 2008-04-15 Elan Microelectronics Corporation Class AB operational buffer
US20060170498A1 (en) * 2004-12-31 2006-08-03 Lionel Portmann Class AB operational buffer
US20060192587A1 (en) * 2005-02-25 2006-08-31 Dipankar Bhattacharya Self-bypassing voltage level translator circuit
US7145364B2 (en) * 2005-02-25 2006-12-05 Agere Systems Inc. Self-bypassing voltage level translator circuit
TW200701641A (en) 2005-06-20 2007-01-01 Faraday Tech Corp Pre-buffer level shifter and output buffer apparatus
US20070018623A1 (en) * 2005-07-21 2007-01-25 Agere Systems Inc. Low-dropout regulator with startup overshoot control
US20070159250A1 (en) * 2006-01-06 2007-07-12 Nec Electronics Corporation Differential amplifier, data driver and display device
US20080252375A1 (en) * 2007-04-10 2008-10-16 Raydium Semiconductor Corporation Voltage-clamping device and operational amplifier and design method thereof
US7595690B2 (en) * 2007-04-10 2009-09-29 Raydium Semiconductor Corporation Voltage-clamping device and operational amplifier and design method thereof
US20090278602A1 (en) * 2008-05-09 2009-11-12 Broadcom Corporation Closed loop surge protection technique for differential amplifiers
US20090310385A1 (en) * 2008-06-13 2009-12-17 Dragan Maksimovic Method, apparatus & system for extended switched-mode controller
US8686708B2 (en) * 2009-03-19 2014-04-01 Kabushiki Kaisha Toshiba Switching circuit

Also Published As

Publication number Publication date
US20110181336A1 (en) 2011-07-28
US8487687B2 (en) 2013-07-16
TWI407694B (en) 2013-09-01
TW201126907A (en) 2011-08-01

Similar Documents

Publication Publication Date Title
USRE47743E1 (en) Output buffer circuit and method for avoiding voltage overshoot
US11876510B2 (en) Load driver
JP4921106B2 (en) Buffer circuit
US8159302B2 (en) Differential amplifier circuit
US7863982B2 (en) Driving circuit capable of enhancing response speed and related method
US8044950B2 (en) Driver circuit usable for display panel
US6897726B2 (en) Differential circuit, amplifier circuit, and display device using the amplifier circuit
US8860472B2 (en) Power switch driving circuits and switching mode power supply circuits thereof
KR101507199B1 (en) Differential amplifying circuit
US8604844B2 (en) Output circuit
US8022730B2 (en) Driving circuit with slew-rate enhancement circuit
US8054122B2 (en) Analog switch with a low flatness operating characteristic
US7436261B2 (en) Operational amplifier
US9436023B2 (en) Operational amplifier
US9467108B2 (en) Operational amplifier circuit and method for enhancing driving capacity thereof
US7969217B2 (en) Output buffer with slew-rate enhancement output stage
US20120319736A1 (en) Comparator and method with adjustable speed and power consumption
CN110611497A (en) Comparator and oscillation circuit
JP2005130185A (en) Semiconductor integrated circuit device
US8456211B2 (en) Slew rate control circuit and method thereof and slew rate control device
US20140184307A1 (en) Gate driver having function of preventing shoot-through current
JP5402368B2 (en) Differential amplifier
US8593178B2 (en) CMOS logic circuit

Legal Events

Date Code Title Description
MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8