CN103636002B - 大于沟道长宽比的器件有源沟道长宽比 - Google Patents

大于沟道长宽比的器件有源沟道长宽比 Download PDF

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CN103636002B
CN103636002B CN201180070976.0A CN201180070976A CN103636002B CN 103636002 B CN103636002 B CN 103636002B CN 201180070976 A CN201180070976 A CN 201180070976A CN 103636002 B CN103636002 B CN 103636002B
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T·本杰明
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Abstract

一种包括漏极、沟道、和栅极的器件。所述沟道包围所述漏极并且具有沟道长宽比。所述栅极位于所述沟道之上，以提供具有大于所述沟道长宽比的有源沟道区长宽比的有源沟道区。

Description

大于沟道长宽比的器件有源沟道长宽比
背景技术
集成电路包括由诸如晶体管、二极管、和电阻器之类的电路组件组成的模拟和数字电路。有时，一个组件的功能由另一个组件提供，例如当晶体管被配置成提供二极管或电阻器的功能时。
在一些被称为配比(ratioed)逻辑电路的逻辑电路中，电阻器作为负载而被连接到晶体管。在配比逻辑电路反相器中，电阻式上拉(pull-up)被连接至晶体管下拉(pull-down)。选择电阻式上拉的电阻值以在一个逻辑状态中提供低输出电压并且在另一个逻辑状态中使该输出充电至高输出电压。较高的电阻值提供较低的输出电压并且降低功耗。
在一些半导体工艺中，提供具有较高电阻值的电阻器消耗集成电路芯片上的大量的宝贵的基板面(real estate)。为了减少所使用的基板面的量，能够用晶体管来提供电阻器的功能，例如通过将金属氧化物半导体场效应晶体管(MOSFET)的漏极连接至其栅极。在一些工艺中，用漏极-至-栅极连接的MOSFET来提供较高的电阻值是困难的。
附图说明
图1是图示MOSFET的一个示例的示图。
图2是图示配比逻辑电路反相器的一个示例的示图。
图3是图示半导体芯片中的层的一个示例的示图。
图4A是沿着图4B的线A-A所取的晶体管的截面图。
图4B是图示晶体管的一个示例的俯视图。
图5A是沿着图5B的线B-B所取的晶体管的截面图。
图5B是图示图5A的晶体管的一个示例的俯视图。
图6是图示具有较长的有源(active)沟道长度和较短的无源(inactive)沟道长度的晶体管的一个示例的俯视图。
图7A是图示具有源极区、漏极区、和沟道的衬底的一个示例的示图。
图7B是图示被布置在沟道之上的栅极的一个示例的示图。
图7C是图示被布置在栅极、漏极区、和源极区上的第二介电层的的一个示例的示图。
图7D是图示被蚀刻的第二介电层的一个示例的示图。
图7E是图示被布置在第二介电层、栅极、漏极区、和源极区上的金属1层的一个示例的示图。
图7F是图示在蚀刻金属1层以形成栅极引线(lead)、漏极引线、和源极引线之后的晶体管的一个示例的示图。
具体实施方式
在下面的详细描述中，参考了形成本文的一部分的附图，并且在所述附图中通过图示的方式示出了其中可以实施本发明的特定实施例。在该方面，参考所描述的附图的定向来使用诸如“顶”、“底”、“前”、“后”、“首”、“尾”等之类的方向术语。由于能够以许多不同的定向来安置本发明的实施例的组件，所以方向术语被用于说明的目的并且绝不是限制。要理解的是，可以利用其他实施例，并且可以做出结构或逻辑的改变而不背离本发明的范围。因此，不以限制意义来进行下面的详细描述，并且由所附权利要求来定义本发明的范围。
图1是图示包括具有源极24、漏极26、和沟道28的半导体衬底22的MOSFET20的一个示例的示图。沟道28位于源极24和漏极26之间，并且栅极30位于沟道28之上。介电材料层32被布置在沟道28和栅极30之间。源极24包括N+掺杂区，并且漏极26包括N+掺杂区。沟道28包括位于源极24和漏极26的N+掺杂区之间的p掺杂区。
在操作中，电压被施加于栅极30以在漏极26与源极24之间的沟道28中产生导电通路。通过将漏极26连接至较高的电压并且将源极24连接至例如地的较低的电压，电流从漏极26流向源极24。栅极30处的较低电压使MOSFET20偏向关闭状态，其中电流不在漏极26和源极24之间流动。
在配比逻辑电路中，诸如MOSFET20的晶体管能够被用作晶体管或用来提供电阻器的功能。为了提供电阻器的功能，漏极26被电气耦合至栅极30。如果在漏极26和栅极30处比在源极24处提供了更高的电压，那么电流从漏极26流向源极24。
图2是图示包括第一晶体管42和第二晶体管44的配比逻辑电路反相器40的一个示例的示图。第一和第二晶体管42和44中的每个都与MOSFET20相类似。在另一个示例中，第一晶体管42与MOSFET20相类似，并且第二晶体管44是不同类型的晶体管。
第一晶体管42用作电阻式上拉并且第二晶体管44用作晶体管下拉。第一晶体管42的漏极D1被电气耦合至第一晶体管42的栅极G1以及至46处的VDD。第一晶体管42的源极S1被电气耦合至第二晶体管44的漏极D2以及至48处的输出OUT。第二晶体管44的栅极G2接收50处的输入电压VIN，并且第二晶体管44的源极S2被电气耦合至52处的参考(例如地)。
在操作中，50处的低输入电压VIN使第二晶体管44偏置关闭。第一晶体管42用作电阻式上拉以将48处的输出OUT拉至接近VDD的高电压值。50处的高输入电压VIN使第二晶体管44偏置开启，其将48处的输出OUT拉至低输出电压。该低输出电压基本上等于VDD乘以第二晶体管44的开态电阻与第一晶体管42的电阻和第二晶体管44的开态电阻之和的比值。建造第一晶体管42以提供电阻值，所述电阻值提供低于下一个逻辑阶段的阈值电压的低输出电压。第一晶体管42所提供的较高的电阻值引起较低的输出电压并且减少功耗。通过第一晶体管42提供较高电阻值的一种方式是增大第一晶体管42的沟道长宽比。
图3是图示半导体芯片60中的层的一个示例的示图。在一个示例中，半导体芯片60包括例如图1的MOSFET20的晶体管。在一个示例中，半导体芯片60包括例如图2的配比逻辑电路反相器40的配比逻辑电路。在一个示例中，半导体芯片60被用于喷墨打印头。在一个示例中，半导体芯片60是喷墨控制芯片。
半导体芯片60包括半导体衬底62、氧化层64、多晶硅层66、第一介电层68、金属1层70、第二介电层72、和金属2层74。氧化层64被布置在衬底62上而位于衬底62和多晶硅层66之间。第一介电层68被布置在多晶硅层66上，并且第二介电层72被布置在金属1层70上以将金属1层70与金属2层74相分离。金属1层70和金属2层74提供栅极、漏极、和源极引线以及半导体芯片60中的其他连接。在一个示例中，氧化层64是二氧化硅(SiO2)。在一个示例中，第二介电层72包括氮化硅。在一个示例中，第二介电层72包括碳化硅。在一个示例中，第二介电层72包括氮化硅和碳化硅。
图4A和4B是图示使用图3的半导体芯片60的层的晶体管80的一个示例的示图。
图4A是沿着图4B的线A-A所取的晶体管80的截面图。在一个示例中，图1的MOSFET20与晶体管80相类似。在一个示例中，第一和第二晶体管42和44(图2中所示出的)中的至少一个与晶体管80相类似。在一个示例中，晶体管80被用于喷墨打印头系统。在其他示例中，使用不同工艺的层来产生晶体管80。
晶体管80包括具有N+源极区82a和82b、N+漏极区86、以及包括p沟道区88a和88b的p沟道88的衬底62。漏极区86包括顶面90、底部92、以及位于顶面90和底部92之间的边94。包括沟道区88a和88b的沟道88围绕漏极区86的边94而包围漏极区86。沟道88位于源极区82a和漏极区86之间并且位于源极区82b和漏极区86之间。源极区82a和82b被连接并且是包围沟道88的一个连续源极区82的部分。
沟道88包括围绕漏极区86的闭合曲线结构，其中曲线被定义为与直线类似的对象，但不需要是直的，这限定直线是曲线的特殊情况也就是具有零曲率的曲线。同样，闭合曲线被定义为连接起来并且不具有端点的曲线。包括沟道区88a和88b的沟道88是正方形。在一个示例中，包括沟道区88a和88b的沟道88是长方形而不是正方形。在一个示例中，包括沟道区88a和88b的沟道88具有至少一个圆形的内角或外角。
栅极100被形成于多晶硅层66中并且包括分别位于沟道区88a和88b之上的多晶硅栅极区66a和66b。介电层64位于栅极100和衬底62之间。在一个示例中，介电层64是二氧化硅层。在一个示例中，包括栅极区66a和66b的栅极100与包括沟道区88a和88b的沟道88是相同形状。
介电层68被布置在栅极100、漏极区86、以及包括源极区82a和82b的源极区82之上。接触掩膜被用来在介电层68中产生通孔或孔。孔是用于栅极区66b、漏极区86、和源极区82a的接触孔。金属1层70被布置在介电层68上并且被蚀刻以形成栅极引线102、漏极引线104、和源极引线106。栅极引线102穿过介电层68中的孔而接触栅极区66b，漏极引线104穿过介电层68中的孔而接触漏极区86，并且源极引线106穿过介电层68中的孔而接触源极区82a。
包括栅极区66a和66b的栅极100包括闭合曲线结构，其中曲线被定义为与直线类似的对象，但不需要是直的，这限定直线是曲线的特殊情况也就是具有零曲率的曲线。同样，闭合曲线被定义为连接起来并且不具有端点的曲线。在一个示例中，包括栅极区66a和66b的栅极100是长方形。在一个示例中，包括栅极区66a和66b的栅极100是正方形。在一个示例中，包括栅极区66a和66b的栅极100具有至少一个圆形的内角或外角。
在操作中，电压被施加于栅极引线102以及包括栅极区66a和66b的栅极100，以在漏极区86与源极区82a和82b之间的沟道88中产生导电通路。从漏极区86到源极82的距离为沟道长度Lc。通过漏极引线104和漏极区86被连接至较高的电压并且源极引线106和源极区82a和82b被连接至例如地的较低的电压，电流从漏极区86流向源极区82。栅极引线102和栅极100处的较低的电压使晶体管80偏向关闭状态，其中电流不在漏极区86和源极区82之间流动。
为了提供电阻器的功能，漏极引线104和漏极区86被电气耦合至栅极引线102和栅极100。如果在漏极引线104和栅极引线102处比在源极引线106处提供更高的电压，那么电流从漏极区86流向源极区82。
图4B是图示晶体管80的示例的俯视图。为了清楚起见，图4B中未示出例如介电层68的晶体管80的一些层。如上面所描述的，晶体管80包括栅极100、沟道88、漏极区86、和源极区82。沟道88位于栅极100之下并且由点线来指示。沟道88包围漏极区86并且位于漏极区86和源极区82之间。源极区82包围沟道88。
栅极引线102通过接触孔110(以点线示出)穿过介电层68被连接至栅极100。漏极引线104通过接触孔112(以点线示出)穿过介电层68被连接至漏极区86。源极引线106通过接触孔114(以点线示出)穿过介电层68被连接至源极区82。
栅极100是正方形的闭合曲线结构，其是长方形闭合曲线结构的特殊情况。栅极100包括四条边以及外边和内边中每个上的四个直角(right angle corner)。栅极100具有栅极长度Lg，所述栅极长度Lg是从栅极100的外边116到栅极100的内边118的距离。栅极100具有栅极宽度Wg，所述栅极宽度Wg是在栅极100的内边和外边之间的中点处所测量的围绕栅极100的距离。在一个示例中，栅极长度Lg是在沿着栅极100的内边和外边的不同点处所测量的平均栅极长度。在一个示例中，栅极长度Lg是被用于电路仿真中的等效栅极长度。在一个示例中，栅极宽度Wg是在栅极100的外边所测量的围绕栅极100的距离。在一个示例中，栅极宽度Wg是在栅极100的内边所测量的围绕栅极100的距离。在一个示例中，栅极宽度Wg是被用于电路仿真中的等效栅极宽度。在其他示例中，栅极100能够是另一种形状。
沟道88也是正方形的闭合曲线结构，其是长方形闭合曲线结构的特殊情况。沟道88包括四条边和四个直角。沟道88具有沟道长度Lc，所述沟道长度Lc是从沟道88的外边120到沟道88的内边122的距离。沟道88具有沟道宽度Wc，所述沟道宽度Wc是在沟道88的内边和外边之间的中点处所测量的围绕沟道88的距离，其中沟道宽度Wc与栅极宽度Wg大致相同。在一个示例中，沟道长度Lc是在沿着沟道88的内边和外边的不同点处所测量的平均沟道长度。在一个示例中，沟道长度Lc是被用于电路仿真中的等效沟道长度。在一个示例中，沟道宽度Wc是在沟道88的外边处所测量的围绕沟道88的距离。在一个示例中，沟道宽度Wc是在沟道88的内边处所测量的围绕沟道88的距离。在一个示例中，沟道宽度Wc是被用于电路仿真中的等效沟道宽度。在其他示例中，沟道88能够是另一种形状。
沟道88的基本上全部都是有源沟道区。沟道88的有源沟道区的长宽比等于沟道88的长宽比，其是Lc/Wc。
例如晶体管80的栅极-至-漏极连接的晶体管的电阻值对于例如配比逻辑电路的一些应用而言可能太小。使用晶体管来提供较高的电阻值的一种方式是增大晶体管的沟道长度与沟道宽度之比。增大沟道长度Lc也增大了沟道宽度Wc，这使沟道长宽比方面的增大限制为大约4倍。
图5A和5B是图示晶体管200的一个示例的示图，所述晶体管200通过增大沟道长宽比来增大栅极-至-漏极连接的晶体管的电阻值。使用晶体管200的方法，能够使沟道长宽比增大超过4倍。晶体管200使用图3的半导体芯片60的层。
图5A是沿着图5B的线B-B所取的晶体管200的截面图。在一个示例中，图1的MOSFET20与晶体管200相类似。在一个示例中，第一和第二晶体管42和44(图2中所示出的)中的至少一个与晶体管200相类似。在一个示例中，晶体管200被用于喷墨打印头系统。在其他示例中，使用不同工艺的层来产生晶体管200。
晶体管200包括具有N+源极区202a和202b、N+漏极区206、以及包括p沟道区208a和208b的p沟道208的衬底62。漏极区206包括顶面210、底部212、和位于顶面210和底部212之间的边214。包括沟道区208a和208b的沟道208围绕漏极区206的边214而包围漏极区206。沟道208位于源极区202a和漏极区206之间并且位于源极区202b和漏极区206之间。源极区202a和202b被连接并且是包围沟道208的一个连续源极区202的部分。
沟道208包括围绕漏极区206的闭合曲线结构，其中曲线被定义为与直线类似的对象，但不要求是直的，这限定直线是曲线的特殊情况也就是具有零曲率的曲线。同样，闭合曲线被定义为连接起来并且不具有端点的曲线。包括沟道区208a和208b的沟道208是正方形。在一个示例中，包括沟道区208a和208b的沟道208是长方形而不是正方形。在一个示例中，包括沟道区208a和208b的沟道208具有至少一个圆形的内角或外角。
栅极216(如图5B中所示出的)被形成于沟道208的一个部分之上的多晶硅层66中。沟道208的这一个部分被称为有源沟道区208c(通过栅极216之下的点线来指示)。栅极216不位于沟道208的另一个部分之上，所述沟道208的另一个部分被称为无源沟道区208d，其包括沟道区208a和208b。介电层64位于栅极216与有源沟道区208c中的衬底62之间，并且介电层64位于无源沟道区208d中的衬底62上。在一个示例中，介电层64是二氧化硅层。
介电层68位于栅极216、漏极区206、以及包括源极区202a和202b的源极区202之上。接触掩膜被用来在介电层68中产生通孔或者孔。这些孔是用于栅极216、漏极区206、和源极区202a的接触孔。金属1层70被布置在介电层68上并且被蚀刻以形成栅极引线218、漏极引线220、和源极引线222。栅极引线218穿过介电层68中的孔而接触栅极216，漏极引线220穿过介电层68中的孔而接触漏极区206，并且源极引线222穿过介电层68中的孔而接触源极区202a。
栅极216是具有栅极长度Lg和栅极宽度Wg的长方形栅极。栅极216之下的有源沟道区208c具有有源沟道长度Lca和有源沟道宽度Wca，其中栅极宽度Wg与有源沟道宽度Wca基本相同。在一个示例中，栅极216具有至少一个圆形的内角或外角。在其他示例中，栅极216是另一种形状。
在操作中，电压被施加于栅极引线218和栅极216，以在漏极区206与源极区202之间的有源沟道区208c中产生导电通路。有源沟道区208c中的从漏极区206到源极区202的距离是有源沟道长度Lca。通过漏极引线220和漏极区206被连接至较高的电压并且源极引线222和源极区202被连接至例如地的较低的电压，电流从漏极区206流向源极区202。栅极引线218和栅极216处的较低的电压使晶体管200偏向关闭状态，其中电流不在漏极区206和源极区202之间流动。
为了提供电阻器的功能，漏极引线220和漏极区206被电气耦合至栅极引线218和栅极216。如果在漏极引线220和栅极引线218处比在源极引线222处提供更高的电压，电流从漏极区206流向源极区202。在另一个示例中，为了提供电阻器的功能，漏极引线220和漏极区206能够被电气耦合至例如VDD的高电压，并且栅极引线218和栅极216能够被电气耦合至来自前一阶段的控制输出，所述控制输出能够被设为高电压。
图5B图示晶体管200的示例的俯视图。为了清楚起见，图5B中未示出例如介电层68的晶体管200的一些层。如上面所描述的，晶体管200包括栅极216、沟道208、漏极区206、和源极区202。有源沟道区208c位于栅极216之下并且由点线来指示。沟道208包围漏极区206并且位于漏极区206和源极区202之间。源极区202包围沟道208。
栅极引线218通过接触孔224(以点线示出)穿过介电层68被连接至栅极216。漏极引线220通过接触孔226(以点线示出)穿过介电层68被连接至漏极区206。源极引线222通过接触孔228(以点线示出)穿过介电层68被连接至源极区202。
栅极216是具有四条边和四个直角的长方形栅极。栅极216具有栅极长度Lg，所述栅极长度Lg是从一边230到另一边232的距离。栅极216具有栅极宽度Wg，所述栅极长度Wg是从一边234到另一边236的距离。在一个示例中，栅极长度Lg是在沿着在漏极206和源极202旁边的栅极216的各边的不同点处所测量的平均栅极长度。在一个示例中，栅极长度Lg是被用于电路仿真中的等效栅极长度。在其他示例中，栅极216能够是另一种形状。
沟道208包括有源沟道区208c和无源沟道区208d。有源沟道区208c是栅极216之下的具有四条边和四个直角的长方形沟道。有源沟道区208c具有有源沟道长度Lca，所述有源沟道长度Lca是从一边238到另一边240的距离。有源沟道区208c具有有源沟道宽度Wca，所述有源沟道宽度Wca是从一边234到另一边236的距离，其中栅极宽度Wg与有源沟道宽度Wca基本相同。在一个示例中，有源沟道长度Lca是在沿着在漏极206和源极202旁边的有源沟道区208c的各边的不同点处所测量的平均沟道长度。在一个示例中，有源沟道长度Lca是被用于电路仿真中的等效沟道长度。在其他示例中，有源沟道区208c能够是另一种形状。
包括有源沟道区208c和无源沟道区208d的沟道208具有沟道长度Lc，所述沟道长度Lc是从漏极206到源极202的距离。包括有源沟道区208c和无源沟道区208d的沟道208具有沟道宽度Wc，所述沟道宽度Wc是在沟道208的内边和外边之间的中点处所测量的围绕沟道208的距离。在一个示例中，沟道长度Lc是在沿着漏极206和源极202的不同点处所测量的平均沟道长度。在一个示例中，沟道长度Lc是被用于电路仿真中的等效沟道长度。在一个示例中，沟道宽度Wc是在沟道208的外边处所测量的围绕沟道208的距离。在一个示例中，沟道宽度Wc是在沟道208的内边处所测量的围绕沟道208的距离。在一个示例中，沟道宽度Wc是被用于电路仿真中的等效沟道宽度。
在晶体管200中，有源沟道长度Lca与沟道长度Lc基本相等，并且有源沟道宽度Wca小于沟道宽度Wc。因此，有源沟道长宽比Lca/Wca大于沟道长宽比Lc/Wc。
晶体管200包括由沟道208所包围的漏极206，以在不包括场氧化层的工艺中隔离漏极206。栅极216增大栅极长宽比和有源沟道长宽比，这增大栅极-至-漏极连接的晶体管200的电阻值。使用该方法，能够使有源沟道长宽比增大超过4倍。为了减少被用于半导体芯片上的基板面的量，能够增大有源沟道长度Lca，同时在无源沟道区208d中提供被最小化尺寸的沟道长度。
图6是图示具有较长的有源沟道长度Lca和较短的无源沟道长度Lci的晶体管300的一个示例的俯视图。较长的有源沟道长度Lca增大有源沟道长宽比Lca/Wca，这增大栅极-至-漏极连接的晶体管的电阻值。较短的无源沟道长度Lci减少由晶体管300在半导体芯片上所使用的基面板的量。使用该方法，能够增大有源沟道长宽比以提供更高的电阻值，并且能够使晶体管的轮廓最小化以减小尺寸。使用图3中所描绘的工艺来制造晶体管300，包括图3的半导体芯片60的各层。为了清楚起见，图6中未示出例如介电层68的这些层中的一些。晶体管300与晶体管200相类似。
晶体管300包括栅极302、沟道304、漏极区306、和源极区308。有源沟道区304a位于栅极302之下并且由点线来指示。沟道304包围漏极区306并且位于漏极区306和源极区308之间。源极区308包围沟道304。
栅极引线310通过接触孔312(以点线示出)穿过介电层68被连接至栅极302。漏极引线314通过接触孔316(以点线示出)穿过介电层68被连接至漏极区306。源极引线318通过接触孔320(以点线示出)穿过介电层68被连接至源极区308。
栅极302是具有四条边和四个直角的长方形栅极。栅极302具有栅极长度Lg，所述栅极长度Lg是从一边322到另一边324的距离。栅极302具有栅极宽度Wg，所述栅极宽度Wg是从一边326到另一边328的距离。在一个示例中，栅极长度Lg是在沿着在漏极306和源极308旁边的栅极302的各边的不同点处所测量的平均栅极长度。在一个示例中，栅极长度Lg是被用于电路仿真中的等效栅极长度。在其他示例中，栅极302能够是另一种形状。
沟道304包括有源沟道区304a和无源沟道区304b。有源沟道区304a是在栅极302之下的具有四条边和四个直角的长方形沟道。有源沟道区304a具有有源沟道长度Lca，所述有源沟道长度Lca是从一边330到另一边332的距离。有源沟道区304a具有有源沟道宽度Wca，所述有源沟道宽度Wca是从一边326和另一边328的距离，其中栅极宽度Wg与有源沟道宽度Wca基本相同。在一个示例中，有源沟道长度Lca是在沿着在漏极306和源极308旁边的有源沟道区304a的各边的不同点处所测量的平均沟道长度。在一个示例中，有源沟道长度Lca是被用于电路仿真中的等效沟道长度。在其他示例中，有源沟道区304a能够是另一种形状。
无源沟道区304b具有无源沟道长度Lci，所述无源沟道长度Lci是从漏极区306到无源沟道区304b的外边的距离。无源沟道长度Lci短于有源沟道长度Lca以减小晶体管300的尺寸并且在半导体芯片上使用更少的基面板。有源沟道长度Lca长于无源沟道长度Lci，以增大有源沟道长宽比Lca/Wca，这增大栅极-至-漏极连接的晶体管300的电阻值。
包括有源沟道区304a和无源沟道区304b的沟道304具有沟道宽度Wc，所述沟道宽度Wc是在沟道304的内边和外边之间的中点处所测量的围绕沟道304的距离。包括有源沟道区304a和无源沟道区304b的沟道304具有沟道长度Lc，所述沟道长度Lc与从漏极306到源极308的距离以及有源沟道长度Lca以及无源沟道长度Lci相对应。在一个示例中，沟道长度Lc等于(Lca+3Lci)/4。在一个示例中，沟道长度Lc是在沿着漏极206和源极202的不同点处所测量的平均沟道长度。在一个示例中，沟道长度Lc是被用于电路仿真中的等效沟道长度。在一个示例中，沟道宽度Wc是在沟道304的外边处所测量的围绕沟道304的距离。在一个示例中，沟道宽度Wc是在沟道304的内边处所测量的围绕沟道304的距离。在一个示例中，沟道宽度Wc是被用于电路仿真中的等效沟道宽度。
在晶体管300中，有源沟道长度Lca大于沟道长度Lc，并且有源沟道宽度Wca小于沟道宽度Wc。因此，有源沟道长宽比Lca/Wca大于沟道长宽比Lc/Wc。
晶体管300包括由沟道304所包围的漏极306，以在不包括场氧化层的工艺中隔离漏极306。栅极302增大栅极长宽比和有源沟道长宽比，这增大栅极-至-漏极连接的晶体管300的电阻值。使用该方法，能够增大有源沟道长宽比，并且使在半导体芯片上所使用的基板面的量最小化。
图7A-7F是图示制造晶体管400的方法的一个示例的示图。晶体管400与图5A和5B的晶体管200以及图6的晶体管300相类似。
图7A是图示具有N+源极区404a和404b、N+漏极区406、以及包括p沟道区408a和408b的p沟道408的衬底402的一个示例的示图。漏极区406包括顶面410、底部412、和位于顶面410和底部412之间的边414。包括沟道区408a和408b的沟道408围绕漏极区406的边414而包围漏极区406。沟道408位于源极区404a和漏极区406之间并且位于源极区404b和漏极区406之间。源极区404a和404b被连接并且是包围沟道408的一个连续源极区404的部分。
沟道408包括围绕漏极区406的闭合曲线结构，其中曲线被定义为与直线类似的对象，但不需要是直的，这限定直线是曲线的特殊情况也就是具有零曲率的曲线。同样，闭合曲线被定义为连接起来并且不具有端点的曲线。在一个示例中，沟道408以统一的沟道长度Lc来包围漏极区406。在一个示例中，沟道408以不统一的沟道长度Lc来包围漏极区406。在一个示例中，包括沟道区408a和408b的沟道408是正方形。在一个示例中，包括沟道区408a和408b的沟道408是长方形而不是正方形。在一个示例中，包括沟道区408a和408b的沟道408具有至少一个圆形的内角或外角。
图7B是图示被布置于沟道408之上的栅极416的一个示例的示图。介电层64被布置于衬底402上，并且多晶硅层66被布置于介电层64上。介电层64被图案化以保留在沟道408上并且包括沟道区408a上的介电层64a和沟道区408b上的介电层64b。栅极416被形成于多晶硅层66中并且包括分别位于沟道区408a和408b之上的多晶硅栅极区66a和66b。介电层64位于栅极416和衬底402之间。在一个示例中，介电层64是二氧化硅层。在一个示例中，栅极416与沟道408是相同形状。
图7C是图示被布置于栅极416、漏极区406、以及包括源极区404a和404b的源极区404上的第二介电层68的一个示例的示图。
图7D是图示在通过接触掩膜来蚀刻介电层68以在介电层68中产生孔之后的被蚀刻的介电层68的一个示例的示图。在介电层68中蚀刻接触孔以与栅极416、漏极区406、和源极区404a进行接触。穿过例如晶体管200中的有源沟道区208c和晶体管300中的有源沟道区304a之类的有源沟道区之上的介电层68来蚀刻用于栅极416的接触孔。还通过包括沟道区408a和408b的无源沟道区之上的部分栅极416之上的接触掩膜来将介电层68蚀刻掉，并且无源沟道区例如是晶体管200中的无源沟道区208d和晶体管300中的无源沟道区304b。
图7E是图示被布置在介电层68、栅极416、漏极区406、和源极区404上的金属1层70的一个示例的示图。金属1层70穿过栅极接触孔且在无源沟道区之上接触栅极416。金属1层70穿过漏极接触孔而接触漏极区406以及穿过源极区404a之上的源极接触孔而接触源极区404。
图7F是图示在蚀刻金属1层70以形成栅极引线(未示出)、漏极引线418、和源极引线420之后的晶体管400的一个示例的示图。在光刻工艺中不被保护的区域中(包括在有源沟道区之上)金属1层70被向下蚀刻掉直到介电层68。在无源沟道区之上金属1层70和栅极416被向下蚀刻掉直到包括介电层64a和64b的介电层64。
栅极引线穿过晶体管400的有源沟道区之上的介电层68中的接触孔而接触栅极416。漏极引线418穿过介电层68中的接触孔而接触漏极区406，并且源极引线420穿过源极区404a之上的介电层68中的接触孔而接触源极区404。
将金属1层70和部分栅极416蚀刻掉产生了晶体管400中的有源沟道区和无源沟道区，其中有源沟道区具有在将大于金属1层70和部分栅极416蚀刻掉之前的晶体管400的沟道长宽比的有源沟道区长宽比。在一个示例中，将金属1层70和部分栅极416蚀刻掉产生了有源沟道区和无源沟道区，这在有源沟道区中提供较长的沟道长度并且在无源沟道区中提供较短的沟道长度。
晶体管400包括由沟道408所包围的漏极406，以在不包括场氧化层的工艺中隔离漏极406。栅极416被蚀刻以增大栅极长宽比和有源沟道长宽比，这增大栅极-至-漏极连接的晶体管400的电阻值。使用该方法，能够增大有源沟道长宽比并且使半导体芯片上所使用的基板面的量最小化。
尽管本文已图示和描述了特定实施例，但是本领域技术人员将理解的是，各种替代和/或等价实现可以代替所示出和描述的特定实施例而不背离本发明的范围。本申请意在涵盖本文所讨论的特定实施例的任何变形或变化。因此，意在仅由权利要求书以及其等价物来限定本发明。

Claims (14)

1.一种半导体器件，包括：
漏极；
包围所述漏极并且具有沟道长宽比的沟道；以及
位于所述沟道之上的栅极，以提供具有大于所述沟道长宽比的有源沟道区长宽比的有源沟道区；
其中所述漏极电耦合到所述栅极。
2.如权利要求1所述的器件，其中所述沟道围绕漏极而具有统一的沟道长度。
3.如权利要求1所述的器件，其中所述沟道围绕漏极而具有不统一的沟道长度。
4.如权利要求1所述的器件，其中所述沟道包括无源沟道区，并且所述沟道在有源沟道区中具有较长的沟道长度并且在无源沟道区中具有较短的沟道长度。
5.如权利要求1所述的器件，包括所述栅极上的介电层以及在所述栅极之上并且在所述介电层上的金属，其中所述金属包括穿过所述介电层而接触所述栅极的栅极引线以及穿过所述介电层而接触所述漏极的漏极引线。
6.如权利要求1所述的器件，包括所述沟道和所述栅极之间的二氧化硅层以及包围所述沟道的源极。
7.一种半导体器件，包括:
漏极；
包围所述漏极的沟道，并且所述沟道包含具有有源沟道区长度的有源沟道区以及具有小于所述有源沟道区长度的无源沟道区长度的无源沟道区；以及
位于所述有源沟道区之上的栅极；
其中所述漏极电耦合到所述栅极。
8.如权利要求7所述的半导体器件，其中所述沟道具有沟道长宽比并且所述栅极具有大于所述沟道长宽比的栅极长宽比。
9.如权利要求7所述的半导体器件，包括所述栅极上的介电层以及在所述栅极之上并且在所述介电层上的金属，其中所述金属包括穿过所述介电层而接触所述栅极的栅极引线和穿过所述介电层而接触所述漏极的漏极引线。
10.如权利要求7所述的半导体器件，其中所述栅极被电气连接至所述漏极，以在配比逻辑电路中提供电阻器上拉。
11.一种制造器件的方法，包括：
以沟道来包围漏极；
在所述沟道之上布置栅极；
在所述栅极和所述漏极上布置介电层；
蚀刻所述介电层以提供漏极接触并且将所述栅极的第一部分和所述栅极的第二部分上的介电层蚀刻掉以提供栅极接触；
在所述器件上布置金属以通过所述栅极接触而接触所述栅极并且通过所述漏极接触而接触所述漏极；以及
蚀刻金属以提供栅极引线和漏极引线并且将所述栅极的第二部分和所述栅极的第二部分上的金属蚀刻掉；
其中所述沟道具有沟道长宽比，并且蚀刻金属将所述栅极的第二部分蚀刻掉以提供大于所述沟道长宽比的有源沟道区长宽比。
12.如权利要求11所述的方法，其中蚀刻金属包括：
将所述栅极的第二部分蚀刻掉以提供有源沟道区和无源沟道区。
13.如权利要求11所述的方法，其中蚀刻金属包括：
将所述栅极的第二部分蚀刻掉以提供有源沟道区和无源沟道区，这在所述有源沟道区中提供较长的沟道长度并且在所述无源沟道区中提供较短的沟道长度。
14.如权利要求11所述的方法，其中以沟道包围漏极包括：
以统一沟道长度的沟道来包围所述漏极。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9716144B2 (en) 2014-12-19 2017-07-25 General Electric Company Semiconductor devices having channel regions with non-uniform edge
US10501003B2 (en) * 2015-07-17 2019-12-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, lighting device, and vehicle
US10073943B2 (en) * 2015-09-25 2018-09-11 Nxp Usa, Inc. Gate length upsizing for low leakage standard cells

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1863088A2 (en) * 2006-06-02 2007-12-05 NEC Electronics Corporation FET semiconductor device with partial annular gate electrodes
CN101728382A (zh) * 2008-10-21 2010-06-09 北大方正集团有限公司 一种功率器件芯片

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5156989A (en) * 1988-11-08 1992-10-20 Siliconix, Incorporated Complementary, isolated DMOS IC technology
US5258636A (en) * 1991-12-12 1993-11-02 Power Integrations, Inc. Narrow radius tips for high voltage semiconductor devices with interdigitated source and drain electrodes
US5811863A (en) * 1994-11-02 1998-09-22 Lsi Logic Corporation Transistors having dynamically adjustable characteristics
US6049104A (en) 1997-11-28 2000-04-11 Magepower Semiconductor Corp. MOSFET device to reduce gate-width without increasing JFET resistance
US6773997B2 (en) 2001-07-31 2004-08-10 Semiconductor Components Industries, L.L.C. Method for manufacturing a high voltage MOSFET semiconductor device with enhanced charge controllability
US6798022B1 (en) * 2003-03-11 2004-09-28 Oki Electric Industry Co., Ltd. Semiconductor device with improved protection from electrostatic discharge
US7196375B2 (en) 2004-03-16 2007-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. High-voltage MOS transistor
US7176125B2 (en) 2004-07-23 2007-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a static random access memory with a buried local interconnect
KR100680958B1 (ko) 2005-02-23 2007-02-09 주식회사 하이닉스반도체 피모스 트랜지스터의 제조방법
US9466596B2 (en) * 2006-12-28 2016-10-11 Marvell World Trade Ltd. Geometry of MOS device with low on-resistance
US20080246062A1 (en) 2007-03-26 2008-10-09 Elizabeth Brauer Semiconductor based controllable high resistance device
US7737526B2 (en) 2007-03-28 2010-06-15 Advanced Analogic Technologies, Inc. Isolated trench MOSFET in epi-less semiconductor sustrate
US7598147B2 (en) * 2007-09-24 2009-10-06 International Business Machines Corporation Method of forming CMOS with Si:C source/drain by laser melting and recrystallization
KR101405310B1 (ko) * 2007-09-28 2014-06-12 삼성전자 주식회사 반도체 집적 회로 장치 및 그 제조 방법
US7741659B2 (en) * 2007-10-25 2010-06-22 United Microelectronics Corp. Semiconductor device
JP5581907B2 (ja) * 2010-09-01 2014-09-03 株式会社リコー 半導体集積回路及び半導体集積回路装置
US20140103440A1 (en) * 2012-10-15 2014-04-17 Texas Instruments Incorporated I-shaped gate electrode for improved sub-threshold mosfet performance

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1863088A2 (en) * 2006-06-02 2007-12-05 NEC Electronics Corporation FET semiconductor device with partial annular gate electrodes
CN101728382A (zh) * 2008-10-21 2010-06-09 北大方正集团有限公司 一种功率器件芯片

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US20140042505A1 (en) 2014-02-13
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