DE69124291D1 - Halbleiterspeicher mit verbesserter Leseanordnung - Google Patents

Halbleiterspeicher mit verbesserter Leseanordnung

Info

Publication number
DE69124291D1
DE69124291D1 DE69124291T DE69124291T DE69124291D1 DE 69124291 D1 DE69124291 D1 DE 69124291D1 DE 69124291 T DE69124291 T DE 69124291T DE 69124291 T DE69124291 T DE 69124291T DE 69124291 D1 DE69124291 D1 DE 69124291D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
reading arrangement
improved reading
improved
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69124291T
Other languages
English (en)
Other versions
DE69124291T2 (de
Inventor
Takeo Fujii
Toshio Komuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69124291D1 publication Critical patent/DE69124291D1/de
Application granted granted Critical
Publication of DE69124291T2 publication Critical patent/DE69124291T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69124291T 1990-06-15 1991-06-14 Halbleiterspeicher mit verbesserter Leseanordnung Expired - Fee Related DE69124291T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2156676A JP2611504B2 (ja) 1990-06-15 1990-06-15 半導体メモリ

Publications (2)

Publication Number Publication Date
DE69124291D1 true DE69124291D1 (de) 1997-03-06
DE69124291T2 DE69124291T2 (de) 1997-07-10

Family

ID=15632883

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69124291T Expired - Fee Related DE69124291T2 (de) 1990-06-15 1991-06-14 Halbleiterspeicher mit verbesserter Leseanordnung

Country Status (5)

Country Link
US (1) US5274598A (de)
EP (1) EP0464426B1 (de)
JP (1) JP2611504B2 (de)
KR (1) KR950000757B1 (de)
DE (1) DE69124291T2 (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3319610B2 (ja) * 1991-11-22 2002-09-03 日本テキサス・インスツルメンツ株式会社 信号伝達回路
US5475642A (en) * 1992-06-23 1995-12-12 Taylor; David L. Dynamic random access memory with bit line preamp/driver
JP3279681B2 (ja) * 1992-09-03 2002-04-30 株式会社日立製作所 半導体装置
US5715189A (en) * 1993-04-13 1998-02-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having hierarchical bit line arrangement
JPH0757464A (ja) * 1993-08-10 1995-03-03 Oki Electric Ind Co Ltd 半導体記憶回路
JP3304635B2 (ja) 1994-09-26 2002-07-22 三菱電機株式会社 半導体記憶装置
JP3270294B2 (ja) * 1995-01-05 2002-04-02 株式会社東芝 半導体記憶装置
US5734620A (en) * 1995-04-05 1998-03-31 Micron Technology, Inc. Hierarchical memory array structure with redundant components having electrically isolated bit lines
US5600602A (en) * 1995-04-05 1997-02-04 Micron Technology, Inc. Hierarchical memory array structure having electrically isolated bit lines for temporary data storage
JP2900854B2 (ja) * 1995-09-14 1999-06-02 日本電気株式会社 半導体記憶装置
KR0186094B1 (ko) * 1995-10-12 1999-05-15 구본준 메모리 소자내의 메인앰프의 배치구조
JPH09251782A (ja) * 1996-03-14 1997-09-22 Fujitsu Ltd 半導体記憶装置
US5995403A (en) * 1996-03-29 1999-11-30 Nec Corporation DRAM having memory cells each using one transfer gate and one capacitor to store plural bit data
US5668766A (en) * 1996-05-16 1997-09-16 Intel Corporation Method and apparatus for increasing memory read access speed using double-sensing
JP3291206B2 (ja) * 1996-09-17 2002-06-10 富士通株式会社 半導体記憶装置
US5790467A (en) * 1996-11-25 1998-08-04 Texas Instruments Incorporated Apparatus and method for a direct-sense sense amplifier with a single read/write control line
KR100221629B1 (ko) * 1996-12-28 1999-09-15 구본준 디알에이엠의 데이터 억세스 장치
JPH11306762A (ja) * 1998-04-20 1999-11-05 Mitsubishi Electric Corp 半導体記憶装置
WO2001057875A1 (fr) * 2000-02-04 2001-08-09 Hitachi, Ltd. Dispositif semi-conducteur
DE10139725B4 (de) * 2001-08-13 2006-05-18 Infineon Technologies Ag Integrierter dynamischer Speicher sowie Verfahren zum Betrieb eines integrierten dynamischen Speichers
KR100451762B1 (ko) * 2001-11-05 2004-10-08 주식회사 하이닉스반도체 불휘발성 강유전체 메모리 장치 및 그 구동방법
US6721220B2 (en) * 2002-07-05 2004-04-13 T-Ram, Inc. Bit line control and sense amplification for TCCT-based memory cells
JPWO2004042821A1 (ja) 2002-11-08 2006-03-09 株式会社日立製作所 半導体記憶装置
JP4203384B2 (ja) * 2003-09-11 2008-12-24 パナソニック株式会社 半導体装置
KR100611404B1 (ko) * 2004-07-27 2006-08-11 주식회사 하이닉스반도체 메인 증폭기 및 반도체 장치
US7257042B2 (en) * 2006-01-12 2007-08-14 International Business Machines Corporation Enhanced sensing in a hierarchical memory architecture
KR100806607B1 (ko) * 2006-09-01 2008-02-25 주식회사 하이닉스반도체 반도체 메모리 장치
JP5452348B2 (ja) * 2009-07-27 2014-03-26 ルネサスエレクトロニクス株式会社 半導体記憶装置
US9792967B1 (en) * 2016-06-13 2017-10-17 International Business Machines Corporation Managing semiconductor memory array leakage current

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51113545A (en) * 1975-03-31 1976-10-06 Hitachi Ltd Memory
JPS61142591A (ja) * 1984-12-13 1986-06-30 Toshiba Corp 半導体記憶装置
JPS6363197A (ja) * 1986-09-03 1988-03-19 Toshiba Corp 半導体記憶装置
US4819207A (en) * 1986-09-30 1989-04-04 Kabushiki Kaisha Toshiba High-speed refreshing rechnique for highly-integrated random-access memory
JP2618938B2 (ja) * 1987-11-25 1997-06-11 株式会社東芝 半導体記憶装置

Also Published As

Publication number Publication date
EP0464426B1 (de) 1997-01-22
JP2611504B2 (ja) 1997-05-21
KR920001542A (ko) 1992-01-30
DE69124291T2 (de) 1997-07-10
EP0464426A1 (de) 1992-01-08
US5274598A (en) 1993-12-28
JPH0447584A (ja) 1992-02-17
KR950000757B1 (ko) 1995-01-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee