DE68929068T2 - Integrierte Halbleiterschaltungsanordnung vom "Masterslice"-Typ - Google Patents

Integrierte Halbleiterschaltungsanordnung vom "Masterslice"-Typ

Info

Publication number
DE68929068T2
DE68929068T2 DE68929068T DE68929068T DE68929068T2 DE 68929068 T2 DE68929068 T2 DE 68929068T2 DE 68929068 T DE68929068 T DE 68929068T DE 68929068 T DE68929068 T DE 68929068T DE 68929068 T2 DE68929068 T2 DE 68929068T2
Authority
DE
Germany
Prior art keywords
hole
wirings
holes
wiring
impurity region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68929068T
Other languages
German (de)
English (en)
Other versions
DE68929068D1 (de
Inventor
Yoshio Hirose
Shigeki Kawahara
Ataru Kumagai
Takeshi Sasaki
Shinji Sato
Koichi Yamashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP63100631A external-priority patent/JP2526269B2/ja
Priority claimed from JP63180953A external-priority patent/JPH0230163A/ja
Priority claimed from JP63180954A external-priority patent/JPH0230164A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE68929068D1 publication Critical patent/DE68929068D1/de
Publication of DE68929068T2 publication Critical patent/DE68929068T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE68929068T 1988-04-22 1989-04-20 Integrierte Halbleiterschaltungsanordnung vom "Masterslice"-Typ Expired - Fee Related DE68929068T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP63100631A JP2526269B2 (ja) 1988-04-22 1988-04-22 マスタスライス方法
JP63180953A JPH0230163A (ja) 1988-07-20 1988-07-20 マスタスライス型半導体集積回路装置およびその製造方法
JP63180954A JPH0230164A (ja) 1988-07-20 1988-07-20 マスタスライス型半導体集積回路装置およびその製造方法

Publications (2)

Publication Number Publication Date
DE68929068D1 DE68929068D1 (de) 1999-10-14
DE68929068T2 true DE68929068T2 (de) 1999-12-23

Family

ID=27309268

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68929068T Expired - Fee Related DE68929068T2 (de) 1988-04-22 1989-04-20 Integrierte Halbleiterschaltungsanordnung vom "Masterslice"-Typ

Country Status (4)

Country Link
US (1) US5506162A (enExample)
EP (2) EP0338817B1 (enExample)
KR (1) KR920008419B1 (enExample)
DE (1) DE68929068T2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5252507A (en) * 1990-03-30 1993-10-12 Tactical Fabs, Inc. Very high density wafer scale device architecture
US5315130A (en) * 1990-03-30 1994-05-24 Tactical Fabs, Inc. Very high density wafer scale device architecture
US5691218A (en) * 1993-07-01 1997-11-25 Lsi Logic Corporation Method of fabricating a programmable polysilicon gate array base cell structure
US6242767B1 (en) 1997-11-10 2001-06-05 Lightspeed Semiconductor Corp. Asic routing architecture
KR100313280B1 (ko) 1999-10-25 2001-11-07 한신혁 반도체 장치의 전도배선 마스크 제조방법
US6613611B1 (en) 2000-12-22 2003-09-02 Lightspeed Semiconductor Corporation ASIC routing architecture with variable number of custom masks
US6885043B2 (en) * 2002-01-18 2005-04-26 Lightspeed Semiconductor Corporation ASIC routing architecture
JP2006156929A (ja) * 2004-04-19 2006-06-15 Fujitsu Ltd 半導体集積回路及びその設計方法
US8097918B2 (en) * 2009-08-14 2012-01-17 Infineon Technologies Ag Semiconductor arrangement including a load transistor and sense transistor

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3835530A (en) * 1967-06-05 1974-09-17 Texas Instruments Inc Method of making semiconductor devices
US3702025A (en) * 1969-05-12 1972-11-07 Honeywell Inc Discretionary interconnection process
US3861023A (en) * 1973-04-30 1975-01-21 Hughes Aircraft Co Fully repairable integrated circuit interconnections
JPS57133712A (en) * 1981-02-12 1982-08-18 Fujitsu Ltd Constituting method of delay circuit in master slice ic
JPS57211248A (en) * 1981-06-22 1982-12-25 Hitachi Ltd Semiconductor integrated circuit device
DE3276284D1 (en) * 1981-09-10 1987-06-11 Fujitsu Ltd Semiconductor integrated circuit comprising a semiconductor substrate and interconnecting layers
JPS5851538A (ja) * 1981-09-24 1983-03-26 Hitachi Ltd 半導体集積回路装置
JPS5851537A (ja) * 1981-09-24 1983-03-26 Ricoh Co Ltd マスタスライスチツプ
JPS58200570A (ja) * 1982-05-19 1983-11-22 Hitachi Ltd 半導体集積回路装置
GB2122809B (en) * 1982-06-01 1985-10-02 Standard Telephones Cables Ltd Integrated circuit interconnection bus structure
DE3238311A1 (de) * 1982-10-15 1984-04-19 Siemens AG, 1000 Berlin und 8000 München Integrierte halbleiterschaltung in gate-array-technik
US4568961A (en) * 1983-03-11 1986-02-04 Rca Corporation Variable geometry automated universal array
JPS59204254A (ja) * 1983-05-06 1984-11-19 Sumitomo Electric Ind Ltd 多層配線マスタスライスｉｃの製造方法
JPS59220940A (ja) * 1983-05-31 1984-12-12 Toshiba Corp 電子ビ−ムによる半導体装置の内部動作電圧波形の測定方法
US4617193A (en) * 1983-06-16 1986-10-14 Digital Equipment Corporation Planar interconnect for integrated circuits
JPS6022337A (ja) * 1983-07-19 1985-02-04 Toshiba Corp 半導体集積回路
JPS6065547A (ja) * 1983-09-20 1985-04-15 Sharp Corp 半導体装置
JPH0828480B2 (ja) * 1983-09-30 1996-03-21 富士通株式会社 半導体集積回路装置
JPS60144956A (ja) * 1984-01-06 1985-07-31 Oki Electric Ind Co Ltd 半導体装置の製造方法
US4613941A (en) * 1985-07-02 1986-09-23 The United States Of America As Represented By The Secretary Of The Army Routing method in computer aided customization of a two level automated universal array
DE3718598A1 (de) * 1986-06-04 1987-12-10 Mitsubishi Electric Corp Halbleiteranordnung
JPS63275138A (ja) * 1987-05-06 1988-11-11 Nec Corp 集積回路
DE3852692T2 (de) * 1987-10-22 1995-08-03 Matsushita Electronics Corp Integriertes Schaltkreis-Bauelement vom Typ "Master Slice" und dessen Verwendung.
US5185283A (en) * 1987-10-22 1993-02-09 Matsushita Electronics Corporation Method of making master slice type integrated circuit device
JPH02247943A (ja) * 1989-03-20 1990-10-03 Toshiba Corp カラー受像管用シャドウマスクの洗浄方法

Also Published As

Publication number Publication date
EP0338817B1 (en) 1999-09-08
EP0650196A3 (enExample) 1995-05-10
US5506162A (en) 1996-04-09
EP0650196A2 (en) 1995-04-26
DE68929068D1 (de) 1999-10-14
EP0338817A3 (en) 1992-05-06
KR890016667A (ko) 1989-11-29
EP0338817A2 (en) 1989-10-25
KR920008419B1 (ko) 1992-09-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee