DE69524804T2 - Basiszelle für BICMOS und CMOS-Gate-Arrays - Google Patents
Basiszelle für BICMOS und CMOS-Gate-ArraysInfo
- Publication number
- DE69524804T2 DE69524804T2 DE69524804T DE69524804T DE69524804T2 DE 69524804 T2 DE69524804 T2 DE 69524804T2 DE 69524804 T DE69524804 T DE 69524804T DE 69524804 T DE69524804 T DE 69524804T DE 69524804 T2 DE69524804 T2 DE 69524804T2
- Authority
- DE
- Germany
- Prior art keywords
- bicmos
- gate arrays
- basic cell
- cmos gate
- cmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003491 array Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11896—Masterslice integrated circuits using combined field effect/bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/240,411 US5591995A (en) | 1994-05-10 | 1994-05-10 | Base cell for BiCMOS and CMOS gate arrays |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69524804D1 DE69524804D1 (de) | 2002-02-07 |
DE69524804T2 true DE69524804T2 (de) | 2002-08-22 |
Family
ID=22906407
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69524804T Expired - Lifetime DE69524804T2 (de) | 1994-05-10 | 1995-05-04 | Basiszelle für BICMOS und CMOS-Gate-Arrays |
Country Status (6)
Country | Link |
---|---|
US (2) | US5591995A (de) |
EP (1) | EP0683524B1 (de) |
JP (1) | JP3577131B2 (de) |
KR (1) | KR100377892B1 (de) |
DE (1) | DE69524804T2 (de) |
TW (1) | TW268167B (de) |
Families Citing this family (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2720816B2 (ja) * | 1995-03-31 | 1998-03-04 | 日本電気株式会社 | BiMOS集積回路 |
JP3008892B2 (ja) * | 1997-05-28 | 2000-02-14 | 日本電気株式会社 | 半導体装置 |
US6218225B1 (en) * | 1998-05-14 | 2001-04-17 | Texas Instruments Incorporated | Apparatus and method for high density CMOS gate arrays |
US6480032B1 (en) * | 1999-03-04 | 2002-11-12 | Intel Corporation | Gate array architecture |
US6974978B1 (en) * | 1999-03-04 | 2005-12-13 | Intel Corporation | Gate array architecture |
JP3313668B2 (ja) * | 1999-07-07 | 2002-08-12 | エヌイーシーマイクロシステム株式会社 | データ処理装置、情報記憶媒体 |
US6703641B2 (en) * | 2001-11-16 | 2004-03-09 | International Business Machines Corporation | Structure for detecting charging effects in device processing |
US6650563B2 (en) * | 2002-04-23 | 2003-11-18 | Broadcom Corporation | Compact and highly efficient DRAM cell |
US7454892B2 (en) * | 2002-10-30 | 2008-11-25 | Georgia Tech Research Corporation | Systems and methods for detection and control of blowout precursors in combustors using acoustical and optical sensing |
DE102004059673B4 (de) | 2004-12-10 | 2011-02-03 | Infineon Technologies Ag | System on Chip, Belichtungsmaskenanordnung und entsprechendes Herstellungsverfahren |
JP2007173474A (ja) * | 2005-12-21 | 2007-07-05 | Oki Electric Ind Co Ltd | ゲートアレイ |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US8247846B2 (en) | 2006-03-09 | 2012-08-21 | Tela Innovations, Inc. | Oversized contacts and vias in semiconductor chip defined by linearly constrained topology |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US7908578B2 (en) | 2007-08-02 | 2011-03-15 | Tela Innovations, Inc. | Methods for designing semiconductor device with dynamic array section |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US8245180B2 (en) | 2006-03-09 | 2012-08-14 | Tela Innovations, Inc. | Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US8286107B2 (en) | 2007-02-20 | 2012-10-09 | Tela Innovations, Inc. | Methods and systems for process compensation technique acceleration |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
JP5599395B2 (ja) | 2008-07-16 | 2014-10-01 | テラ イノヴェイションズ インコーポレイテッド | 動的アレイアーキテクチャにおけるセル位相整合及び配置の方法及びその実施 |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US7960759B2 (en) * | 2008-10-14 | 2011-06-14 | Arm Limited | Integrated circuit layout pattern for cross-coupled circuits |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0394598B1 (de) * | 1989-04-28 | 1996-03-06 | International Business Machines Corporation | Gate-Array-Zelle, bestehend aus FET's von verschiedener und optimierter Grösse |
US5107147A (en) * | 1989-05-15 | 1992-04-21 | Texas Instruments Incorporated | Base cell for semi-custom circuit with merged technology |
JPH0360072A (ja) * | 1989-07-27 | 1991-03-15 | Nec Corp | ゲートアレイ方式の半導体集積回路装置 |
JP2621529B2 (ja) * | 1990-01-19 | 1997-06-18 | 日本電気株式会社 | バイポーラcmos半導体装置 |
DE4002780C2 (de) * | 1990-01-31 | 1995-01-19 | Fraunhofer Ges Forschung | Basiszelle für eine kanallose Gate-Array-Anordnung |
US5289021A (en) * | 1990-05-15 | 1994-02-22 | Siarc | Basic cell architecture for mask programmable gate array with 3 or more size transistors |
US5055716A (en) * | 1990-05-15 | 1991-10-08 | Siarc | Basic cell for bicmos gate array |
US5068548A (en) * | 1990-05-15 | 1991-11-26 | Siarc | Bicmos logic circuit for basic applications |
US5187556A (en) * | 1990-08-13 | 1993-02-16 | Kawasaki Steel Corporation | Cmos master slice |
US5217915A (en) * | 1991-04-08 | 1993-06-08 | Texas Instruments Incorporated | Method of making gate array base cell |
JP2674378B2 (ja) * | 1991-08-26 | 1997-11-12 | 株式会社日立製作所 | 半導体集積回路装置 |
-
1994
- 1994-05-10 US US08/240,411 patent/US5591995A/en not_active Expired - Lifetime
-
1995
- 1995-04-29 KR KR1019950010902A patent/KR100377892B1/ko not_active IP Right Cessation
- 1995-05-04 DE DE69524804T patent/DE69524804T2/de not_active Expired - Lifetime
- 1995-05-04 EP EP95106723A patent/EP0683524B1/de not_active Expired - Lifetime
- 1995-05-09 JP JP11095595A patent/JP3577131B2/ja not_active Expired - Fee Related
- 1995-05-18 TW TW084104915A patent/TW268167B/zh not_active IP Right Cessation
-
1996
- 1996-05-21 US US08/651,137 patent/US5684311A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5684311A (en) | 1997-11-04 |
EP0683524B1 (de) | 2002-01-02 |
TW268167B (de) | 1996-01-11 |
KR100377892B1 (ko) | 2003-06-27 |
JPH0851353A (ja) | 1996-02-20 |
EP0683524A1 (de) | 1995-11-22 |
DE69524804D1 (de) | 2002-02-07 |
KR950034686A (ko) | 1995-12-28 |
US5591995A (en) | 1997-01-07 |
JP3577131B2 (ja) | 2004-10-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |