DE69522846T2 - Verbesserte Speicheranordnung und Herstellungsverfahren - Google Patents

Verbesserte Speicheranordnung und Herstellungsverfahren

Info

Publication number
DE69522846T2
DE69522846T2 DE69522846T DE69522846T DE69522846T2 DE 69522846 T2 DE69522846 T2 DE 69522846T2 DE 69522846 T DE69522846 T DE 69522846T DE 69522846 T DE69522846 T DE 69522846T DE 69522846 T2 DE69522846 T2 DE 69522846T2
Authority
DE
Germany
Prior art keywords
manufacturing process
memory arrangement
improved memory
improved
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69522846T
Other languages
English (en)
Other versions
DE69522846D1 (de
Inventor
Theodore W Houston
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69522846D1 publication Critical patent/DE69522846D1/de
Publication of DE69522846T2 publication Critical patent/DE69522846T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
DE69522846T 1994-03-28 1995-03-28 Verbesserte Speicheranordnung und Herstellungsverfahren Expired - Lifetime DE69522846T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/219,609 US5544101A (en) 1994-03-28 1994-03-28 Memory device having a latching multiplexer and a multiplexer block therefor

Publications (2)

Publication Number Publication Date
DE69522846D1 DE69522846D1 (de) 2001-10-31
DE69522846T2 true DE69522846T2 (de) 2002-04-11

Family

ID=22819983

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69522846T Expired - Lifetime DE69522846T2 (de) 1994-03-28 1995-03-28 Verbesserte Speicheranordnung und Herstellungsverfahren

Country Status (4)

Country Link
US (1) US5544101A (de)
EP (1) EP0675500B1 (de)
JP (1) JPH07312085A (de)
DE (1) DE69522846T2 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08250674A (ja) * 1995-03-15 1996-09-27 Toshiba Microelectron Corp 半導体記憶装置
US5625302A (en) * 1996-02-08 1997-04-29 International Business Machines Corporation Address buffer for synchronous system
US6087858A (en) * 1998-06-24 2000-07-11 Cypress Semiconductor Corp. Self-timed sense amplifier evaluation scheme
US5978280A (en) * 1998-06-25 1999-11-02 Cypress Semiconductor Corp. Method, architecture and circuit for reducing and/or eliminating small signal voltage swing sensitivity
US5986970A (en) * 1998-06-29 1999-11-16 Cypress Semiconductor Corp. Method, architecture and circuit for writing to a memory
US6122203A (en) * 1998-06-29 2000-09-19 Cypress Semiconductor Corp. Method, architecture and circuit for writing to and reading from a memory during a single cycle
US5946255A (en) * 1998-07-31 1999-08-31 Cypress Semiconductor Corp. Wordline synchronized reference voltage generator
US6067267A (en) * 1998-08-12 2000-05-23 Toshiba America Electronic Components, Inc. Four-way interleaved FIFO architecture with look ahead conditional decoder for PCI applications
US6848058B1 (en) * 1999-06-04 2005-01-25 Ati International Srl Power reduction circuit and method with multi clock branch control
US7343508B2 (en) * 2004-03-05 2008-03-11 Ati Technologies Inc. Dynamic clock control circuit for graphics engine clock and memory clock and method
US7500123B2 (en) 2004-06-28 2009-03-03 Ati Technologies Ulc Apparatus and method for reducing power consumption in a graphics processing device
US7827424B2 (en) * 2004-07-29 2010-11-02 Ati Technologies Ulc Dynamic clock control circuit and method
US7379333B2 (en) * 2004-10-28 2008-05-27 Samsung Electronics Co., Ltd. Page-buffer and non-volatile semiconductor memory including page buffer
US7800621B2 (en) * 2005-05-16 2010-09-21 Ati Technologies Inc. Apparatus and methods for control of a memory controller
KR100809699B1 (ko) * 2006-08-25 2008-03-07 삼성전자주식회사 디스플레이용 데이터 구동 장치, 데이터 출력 장치 및디스플레이용 데이터 구동 방법
KR100824779B1 (ko) * 2007-01-11 2008-04-24 삼성전자주식회사 반도체 메모리 장치의 데이터 출력 경로 및 데이터 출력방법
US9760333B2 (en) * 2009-08-24 2017-09-12 Ati Technologies Ulc Pixel clocking method and apparatus
US9348355B2 (en) 2009-08-24 2016-05-24 Ati Technologies Ulc Display link clocking method and apparatus
US8269525B2 (en) * 2009-11-17 2012-09-18 Ati Technologies Ulc Logic cell having reduced spurious toggling
US8432727B2 (en) * 2010-04-29 2013-04-30 Qualcomm Incorporated Invalid write prevention for STT-MRAM array
US8799685B2 (en) 2010-08-25 2014-08-05 Advanced Micro Devices, Inc. Circuits and methods for providing adjustable power consumption
US8964484B2 (en) * 2012-12-28 2015-02-24 Spansion Llc For test (DFT) read speed through transition detector in built-in self-test (BIST) sort

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4593390A (en) * 1984-08-09 1986-06-03 Honeywell, Inc. Pipeline multiplexer
US4685088A (en) * 1985-04-15 1987-08-04 International Business Machines Corporation High performance memory system utilizing pipelining techniques
JPS61265798A (ja) 1985-05-20 1986-11-25 Fujitsu Ltd 半導体記憶装置
US4932002A (en) * 1988-09-30 1990-06-05 Texas Instruments, Incorporated Bit line latch sense amp
US5214610A (en) * 1989-09-22 1993-05-25 Texas Instruments Incorporated Memory with selective address transition detection for cache operation
US5341488A (en) * 1990-04-11 1994-08-23 Nec Electronics, Inc. N-word read/write access achieving double bandwidth without increasing the width of external data I/O bus
JP2685357B2 (ja) * 1990-12-14 1997-12-03 株式会社東芝 半導体記憶装置
DE69122860T2 (de) * 1991-07-06 1997-04-03 Ibm Multiplexer
EP0895162A3 (de) * 1992-01-22 1999-11-10 Enhanced Memory Systems, Inc. Verbesserte DRAM mit eingebauten Registern
US5357146A (en) * 1992-12-31 1994-10-18 At&T Bell Laboratories Glitch-free clock multiplexer

Also Published As

Publication number Publication date
JPH07312085A (ja) 1995-11-28
EP0675500A1 (de) 1995-10-04
DE69522846D1 (de) 2001-10-31
EP0675500B1 (de) 2001-09-26
US5544101A (en) 1996-08-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition