DE69127663D1 - BICMOS-Gate-Array-Anordnung - Google Patents

BICMOS-Gate-Array-Anordnung

Info

Publication number
DE69127663D1
DE69127663D1 DE69127663T DE69127663T DE69127663D1 DE 69127663 D1 DE69127663 D1 DE 69127663D1 DE 69127663 T DE69127663 T DE 69127663T DE 69127663 T DE69127663 T DE 69127663T DE 69127663 D1 DE69127663 D1 DE 69127663D1
Authority
DE
Germany
Prior art keywords
gate array
array arrangement
bicmos gate
bicmos
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127663T
Other languages
English (en)
Other versions
DE69127663T2 (de
Inventor
Tetsu Nagamatsu
Hiroshi Momose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69127663D1 publication Critical patent/DE69127663D1/de
Publication of DE69127663T2 publication Critical patent/DE69127663T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11896—Masterslice integrated circuits using combined field effect/bipolar technology

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE69127663T 1990-07-19 1991-07-18 BICMOS-Gate-Array-Anordnung Expired - Fee Related DE69127663T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2189462A JP2609746B2 (ja) 1990-07-19 1990-07-19 半導体装置

Publications (2)

Publication Number Publication Date
DE69127663D1 true DE69127663D1 (de) 1997-10-23
DE69127663T2 DE69127663T2 (de) 1998-02-12

Family

ID=16241675

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127663T Expired - Fee Related DE69127663T2 (de) 1990-07-19 1991-07-18 BICMOS-Gate-Array-Anordnung

Country Status (5)

Country Link
US (1) US5629537A (de)
EP (1) EP0467361B1 (de)
JP (1) JP2609746B2 (de)
KR (1) KR940009358B1 (de)
DE (1) DE69127663T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2714996B2 (ja) * 1990-08-08 1998-02-16 三菱電機株式会社 半導体集積回路装置
US7420248B2 (en) * 2005-08-25 2008-09-02 International Business Machines Corporation Programmable random logic arrays using PN isolation
JP7090474B2 (ja) * 2017-06-28 2022-06-24 キヤノン株式会社 記録装置、及び記録ヘッド基板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994861A (ja) * 1982-11-24 1984-05-31 Hitachi Ltd 半導体集積回路装置及びその製造方法
JPS59177945A (ja) * 1983-03-28 1984-10-08 Hitachi Ltd 半導体集積回路装置
JPS6035532A (ja) * 1983-07-29 1985-02-23 Fujitsu Ltd マスタスライス集積回路装置
JPS59112642A (ja) * 1983-11-28 1984-06-29 Hitachi Ltd 半導体集積回路
US4884115A (en) * 1987-02-27 1989-11-28 Siemens Aktiengesellschaft Basic cell for a gate array arrangement in CMOS Technology
JPS6424825A (en) * 1987-07-20 1989-01-26 Mitsubishi Gas Chemical Co Epoxy resin composition
JP2632420B2 (ja) * 1989-02-23 1997-07-23 三菱電機株式会社 半導体集積回路
JPH02290069A (ja) * 1989-04-27 1990-11-29 Nec Ic Microcomput Syst Ltd 大規模集積回路

Also Published As

Publication number Publication date
EP0467361B1 (de) 1997-09-17
DE69127663T2 (de) 1998-02-12
KR940009358B1 (ko) 1994-10-07
US5629537A (en) 1997-05-13
EP0467361A1 (de) 1992-01-22
JP2609746B2 (ja) 1997-05-14
JPH0476950A (ja) 1992-03-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee