DE68919458D1 - Halbleiterspeichereinheit mit einem "flash write"-Betrieb. - Google Patents

Halbleiterspeichereinheit mit einem "flash write"-Betrieb.

Info

Publication number
DE68919458D1
DE68919458D1 DE68919458T DE68919458T DE68919458D1 DE 68919458 D1 DE68919458 D1 DE 68919458D1 DE 68919458 T DE68919458 T DE 68919458T DE 68919458 T DE68919458 T DE 68919458T DE 68919458 D1 DE68919458 D1 DE 68919458D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory unit
flash write
write
flash
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68919458T
Other languages
English (en)
Other versions
DE68919458T2 (de
Inventor
Shigeki Goto
Yoshiharu Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Publication of DE68919458D1 publication Critical patent/DE68919458D1/de
Application granted granted Critical
Publication of DE68919458T2 publication Critical patent/DE68919458T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE68919458T 1988-09-20 1989-09-18 Halbleiterspeichereinheit mit einem "flash write"-Betrieb. Expired - Fee Related DE68919458T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63235696A JPH0283892A (ja) 1988-09-20 1988-09-20 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE68919458D1 true DE68919458D1 (de) 1995-01-05
DE68919458T2 DE68919458T2 (de) 1995-03-30

Family

ID=16989868

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68919458T Expired - Fee Related DE68919458T2 (de) 1988-09-20 1989-09-18 Halbleiterspeichereinheit mit einem "flash write"-Betrieb.

Country Status (5)

Country Link
US (1) US5155705A (de)
EP (1) EP0360526B1 (de)
JP (1) JPH0283892A (de)
KR (1) KR920011002B1 (de)
DE (1) DE68919458T2 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE38379E1 (en) * 1989-08-28 2004-01-06 Hitachi, Ltd. Semiconductor memory with alternately multiplexed row and column addressing
EP0430614B1 (de) * 1989-12-01 1996-02-07 Matsushita Electronics Corporation Halbleiterspeicher dynamischen Typs
JP2547268B2 (ja) * 1990-03-14 1996-10-23 シャープ株式会社 半導体記憶装置の内部アドレス決定装置
JPH04221496A (ja) * 1990-03-29 1992-08-11 Intel Corp 単一基板上に設けられるコンピュータメモリ回路およびコンピュータメモリを消去するためのシーケンスを終らせる方法
JP2963504B2 (ja) * 1990-07-23 1999-10-18 沖電気工業株式会社 半導体記憶装置
JP2704041B2 (ja) * 1990-11-09 1998-01-26 日本電気アイシーマイコンシステム株式会社 半導体メモリ装置
US5289423A (en) * 1990-11-16 1994-02-22 Sgs-Thomson Microelectronics S.R.L. Bank erasable, flash-EPROM memory
JP2623979B2 (ja) * 1991-01-25 1997-06-25 日本電気株式会社 ダイナミック型論理回路
JPH04268287A (ja) * 1991-02-22 1992-09-24 Nec Ic Microcomput Syst Ltd 半導体メモリ回路
JP2837970B2 (ja) * 1991-04-12 1998-12-16 三菱電機株式会社 Ｉｃカード
US5305263A (en) * 1991-06-12 1994-04-19 Micron Technology, Inc. Simplified low power flash write operation
JP3084801B2 (ja) * 1991-06-27 2000-09-04 日本電気株式会社 半導体メモリ装置
JPH0528756A (ja) * 1991-07-24 1993-02-05 Toshiba Corp 半導体記憶装置
US6230233B1 (en) * 1991-09-13 2001-05-08 Sandisk Corporation Wear leveling techniques for flash EEPROM systems
JPH05314763A (ja) * 1992-05-12 1993-11-26 Mitsubishi Electric Corp 半導体記憶装置
JP3280704B2 (ja) * 1992-05-29 2002-05-13 株式会社東芝 半導体記憶装置
US5319606A (en) * 1992-12-14 1994-06-07 International Business Machines Corporation Blocked flash write in dynamic RAM devices
JP3358030B2 (ja) * 1993-01-22 2002-12-16 日本テキサス・インスツルメンツ株式会社 半導体メモリ装置及びその初期化方法
US5388083A (en) * 1993-03-26 1995-02-07 Cirrus Logic, Inc. Flash memory mass storage architecture
US5479638A (en) * 1993-03-26 1995-12-26 Cirrus Logic, Inc. Flash memory mass storage architecture incorporation wear leveling technique
KR940026946A (ko) * 1993-05-12 1994-12-10 김광호 데이타출력 확장방법과 이를 통한 신뢰성있는 유효데이타의 출력이 이루어지는 반도체집적회로
JP3782840B2 (ja) 1995-07-14 2006-06-07 株式会社ルネサステクノロジ 外部記憶装置およびそのメモリアクセス制御方法
US6801979B1 (en) 1995-07-31 2004-10-05 Lexar Media, Inc. Method and apparatus for memory control circuit
US6081878A (en) 1997-03-31 2000-06-27 Lexar Media, Inc. Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US6757800B1 (en) 1995-07-31 2004-06-29 Lexar Media, Inc. Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US6728851B1 (en) 1995-07-31 2004-04-27 Lexar Media, Inc. Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US6411546B1 (en) 1997-03-31 2002-06-25 Lexar Media, Inc. Nonvolatile memory using flexible erasing methods and method and system for using same
US6040997A (en) * 1998-03-25 2000-03-21 Lexar Media, Inc. Flash memory leveling architecture having no external latch
US6374337B1 (en) 1998-11-17 2002-04-16 Lexar Media, Inc. Data pipelining method and apparatus for memory control circuit
ATE372578T1 (de) * 2002-10-28 2007-09-15 Sandisk Corp Automatischer abnutzungsausgleich in einem nicht- flüchtigen speichersystem
JP4753637B2 (ja) * 2005-06-23 2011-08-24 パトレネラ キャピタル リミテッド， エルエルシー メモリ

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4099256A (en) * 1976-11-16 1978-07-04 Bell Telephone Laboratories, Incorporated Method and apparatus for establishing, reading, and rapidly clearing a translation table memory
US4270185A (en) * 1977-06-20 1981-05-26 Motorola Israel Limited Memory control circuitry for a supervisory control system
JPS5785255A (en) * 1980-11-17 1982-05-27 Nec Corp Memory storage for integrated circuit
JPS57118599U (de) * 1981-01-14 1982-07-23
JPS58222489A (ja) * 1982-06-18 1983-12-24 Nec Corp 半導体記憶装置
US4567578A (en) * 1982-09-08 1986-01-28 Harris Corporation Cache memory flush scheme
JPS5958691A (ja) * 1982-09-28 1984-04-04 Fujitsu Ltd Ｉｃメモリ
JPS59178685A (ja) * 1983-03-30 1984-10-09 Toshiba Corp 半導体記憶回路
US4587629A (en) * 1983-12-30 1986-05-06 International Business Machines Corporation Random address memory with fast clear
JPS6148192A (ja) * 1984-08-11 1986-03-08 Fujitsu Ltd 半導体記憶装置
JPS62250593A (ja) * 1986-04-23 1987-10-31 Hitachi Ltd ダイナミツク型ｒａｍ
JP2569010B2 (ja) * 1986-05-21 1997-01-08 株式会社日立製作所 半導体メモリ
US4789967A (en) * 1986-09-16 1988-12-06 Advanced Micro Devices, Inc. Random access memory device with block reset
JPH07118193B2 (ja) * 1986-09-18 1995-12-18 富士通株式会社 半導体記憶装置
JPS63106989A (ja) * 1986-10-24 1988-05-12 Hitachi Ltd 半導体記憶装置

Also Published As

Publication number Publication date
JPH0283892A (ja) 1990-03-23
KR900005444A (ko) 1990-04-14
KR920011002B1 (ko) 1992-12-26
US5155705A (en) 1992-10-13
EP0360526A1 (de) 1990-03-28
EP0360526B1 (de) 1994-11-23
DE68919458T2 (de) 1995-03-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee