DE60335137D1 - Verfahren zum durchtrennung einen halbleiter substrat und verwendung einer schutzschicht für jenes verfahren - Google Patents
Verfahren zum durchtrennung einen halbleiter substrat und verwendung einer schutzschicht für jenes verfahrenInfo
- Publication number
- DE60335137D1 DE60335137D1 DE60335137T DE60335137T DE60335137D1 DE 60335137 D1 DE60335137 D1 DE 60335137D1 DE 60335137 T DE60335137 T DE 60335137T DE 60335137 T DE60335137 T DE 60335137T DE 60335137 D1 DE60335137 D1 DE 60335137D1
- Authority
- DE
- Germany
- Prior art keywords
- etching
- plasma
- separating
- progress
- plasma etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 title abstract 3
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 239000011241 protective layer Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
- 238000005530 etching Methods 0.000 abstract 3
- 239000010410 layer Substances 0.000 abstract 3
- 238000001020 plasma etching Methods 0.000 abstract 3
- 230000001681 protective effect Effects 0.000 abstract 2
- 239000012790 adhesive layer Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Dicing (AREA)
- Drying Of Semiconductors (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Formation Of Insulating Films (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002359051A JP4013753B2 (ja) | 2002-12-11 | 2002-12-11 | 半導体ウェハの切断方法 |
PCT/JP2003/015887 WO2004053981A1 (en) | 2002-12-11 | 2003-12-11 | Method of cutting semiconductor wafer and protective sheet used in the cutting method |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60335137D1 true DE60335137D1 (de) | 2011-01-05 |
Family
ID=32500922
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60335137T Expired - Lifetime DE60335137D1 (de) | 2002-12-11 | 2003-12-11 | Verfahren zum durchtrennung einen halbleiter substrat und verwendung einer schutzschicht für jenes verfahren |
Country Status (9)
Country | Link |
---|---|
US (1) | US7060531B2 (de) |
EP (1) | EP1570519B1 (de) |
JP (1) | JP4013753B2 (de) |
KR (1) | KR100971760B1 (de) |
CN (1) | CN100356549C (de) |
AT (1) | ATE489727T1 (de) |
AU (1) | AU2003295231A1 (de) |
DE (1) | DE60335137D1 (de) |
WO (1) | WO2004053981A1 (de) |
Families Citing this family (55)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI231534B (en) * | 2003-12-11 | 2005-04-21 | Advanced Semiconductor Eng | Method for dicing a wafer |
JP4018096B2 (ja) | 2004-10-05 | 2007-12-05 | 松下電器産業株式会社 | 半導体ウェハの分割方法、及び半導体素子の製造方法 |
JP4288229B2 (ja) * | 2004-12-24 | 2009-07-01 | パナソニック株式会社 | 半導体チップの製造方法 |
TWI267133B (en) * | 2005-06-03 | 2006-11-21 | Touch Micro System Tech | Method of segmenting a wafer |
JP2007180395A (ja) * | 2005-12-28 | 2007-07-12 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
US7871899B2 (en) * | 2006-01-11 | 2011-01-18 | Amkor Technology, Inc. | Methods of forming back side layers for thinned wafers |
JP4997955B2 (ja) * | 2006-12-18 | 2012-08-15 | パナソニック株式会社 | 半導体チップの製造方法 |
JP4840174B2 (ja) * | 2007-02-08 | 2011-12-21 | パナソニック株式会社 | 半導体チップの製造方法 |
KR100828025B1 (ko) * | 2007-06-13 | 2008-05-08 | 삼성전자주식회사 | 웨이퍼 절단 방법 |
US7838424B2 (en) * | 2007-07-03 | 2010-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Enhanced reliability of wafer-level chip-scale packaging (WLCSP) die separation using dry etching |
US7989319B2 (en) * | 2007-08-07 | 2011-08-02 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
US8012857B2 (en) * | 2007-08-07 | 2011-09-06 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
US7781310B2 (en) | 2007-08-07 | 2010-08-24 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
US8859396B2 (en) * | 2007-08-07 | 2014-10-14 | Semiconductor Components Industries, Llc | Semiconductor die singulation method |
CN101374384B (zh) * | 2007-08-24 | 2010-10-06 | 富葵精密组件(深圳)有限公司 | 电路板用粘胶膜的切割方法 |
JP2009260272A (ja) * | 2008-03-25 | 2009-11-05 | Panasonic Corp | 基板の加工方法および半導体チップの製造方法ならびに樹脂接着層付き半導体チップの製造方法 |
JP5218238B2 (ja) | 2009-04-10 | 2013-06-26 | パナソニック株式会社 | 基板の加工方法および半導体チップの製造方法ならびに樹脂接着層付き半導体チップの製造方法 |
JP5246001B2 (ja) * | 2009-04-10 | 2013-07-24 | パナソニック株式会社 | 基板の加工方法および半導体チップの製造方法ならびに樹脂接着層付き半導体チップの製造方法 |
KR101104134B1 (ko) * | 2009-10-30 | 2012-01-13 | 전자부품연구원 | 반도체 칩 패키징 방법 |
TWI430415B (zh) * | 2009-12-01 | 2014-03-11 | Xintec Inc | 晶片封裝體及其製造方法 |
US8384231B2 (en) | 2010-01-18 | 2013-02-26 | Semiconductor Components Industries, Llc | Method of forming a semiconductor die |
US9165833B2 (en) * | 2010-01-18 | 2015-10-20 | Semiconductor Components Industries, Llc | Method of forming a semiconductor die |
US9299664B2 (en) * | 2010-01-18 | 2016-03-29 | Semiconductor Components Industries, Llc | Method of forming an EM protected semiconductor die |
US20110175209A1 (en) * | 2010-01-18 | 2011-07-21 | Seddon Michael J | Method of forming an em protected semiconductor die |
USRE46339E1 (en) * | 2011-03-14 | 2017-03-14 | Plasma-Therm Llc | Method and apparatus for plasma dicing a semi-conductor wafer |
US9343365B2 (en) * | 2011-03-14 | 2016-05-17 | Plasma-Therm Llc | Method and apparatus for plasma dicing a semi-conductor wafer |
US8802545B2 (en) | 2011-03-14 | 2014-08-12 | Plasma-Therm Llc | Method and apparatus for plasma dicing a semi-conductor wafer |
JP5833411B2 (ja) * | 2011-11-11 | 2015-12-16 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法ならびに液晶表示装置 |
US8815706B2 (en) | 2012-01-20 | 2014-08-26 | Infineon Technologies Ag | Methods of forming semiconductor devices |
US9553021B2 (en) * | 2012-09-03 | 2017-01-24 | Infineon Technologies Ag | Method for processing a wafer and method for dicing a wafer |
US9136173B2 (en) | 2012-11-07 | 2015-09-15 | Semiconductor Components Industries, Llc | Singulation method for semiconductor die having a layer of material along one major surface |
US9484260B2 (en) | 2012-11-07 | 2016-11-01 | Semiconductor Components Industries, Llc | Heated carrier substrate semiconductor die singulation method |
KR102029646B1 (ko) * | 2013-01-31 | 2019-11-08 | 삼성전자 주식회사 | 반도체 장치 제조 방법 |
US9299614B2 (en) * | 2013-12-10 | 2016-03-29 | Applied Materials, Inc. | Method and carrier for dicing a wafer |
US9418894B2 (en) | 2014-03-21 | 2016-08-16 | Semiconductor Components Industries, Llc | Electronic die singulation method |
US9112050B1 (en) * | 2014-05-13 | 2015-08-18 | Applied Materials, Inc. | Dicing tape thermal management by wafer frame support ring cooling during plasma dicing |
US9472458B2 (en) * | 2014-06-04 | 2016-10-18 | Semiconductor Components Industries, Llc | Method of reducing residual contamination in singulated semiconductor die |
US9385041B2 (en) | 2014-08-26 | 2016-07-05 | Semiconductor Components Industries, Llc | Method for insulating singulated electronic die |
JP2016207737A (ja) * | 2015-04-17 | 2016-12-08 | 株式会社ディスコ | 分割方法 |
JP6506606B2 (ja) * | 2015-04-27 | 2019-04-24 | 株式会社ディスコ | ウエーハの分割方法 |
JP6516125B2 (ja) * | 2015-09-07 | 2019-05-22 | パナソニックIpマネジメント株式会社 | プラズマ処理方法および電子部品の製造方法 |
JP6492288B2 (ja) * | 2015-10-01 | 2019-04-03 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
JP6492287B2 (ja) * | 2015-10-01 | 2019-04-03 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法および電子部品実装構造体の製造方法 |
GB201518756D0 (en) | 2015-10-22 | 2015-12-09 | Spts Technologies Ltd | Apparatus for plasma dicing |
JP6575874B2 (ja) * | 2016-03-09 | 2019-09-18 | パナソニックIpマネジメント株式会社 | 素子チップの製造方法 |
KR101938306B1 (ko) * | 2016-04-18 | 2019-01-14 | 최상준 | 건식 에칭장치의 제어방법 |
US10366923B2 (en) | 2016-06-02 | 2019-07-30 | Semiconductor Components Industries, Llc | Method of separating electronic devices having a back layer and apparatus |
US10373869B2 (en) | 2017-05-24 | 2019-08-06 | Semiconductor Components Industries, Llc | Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus |
CN111201482A (zh) * | 2017-11-30 | 2020-05-26 | 深圳市柔宇科技有限公司 | 显示屏保护结构、显示组件及切割方法、贴膜方法 |
TWI825080B (zh) | 2018-03-30 | 2023-12-11 | 日商琳得科股份有限公司 | 半導體晶片的製造方法 |
US10916474B2 (en) * | 2018-06-25 | 2021-02-09 | Semiconductor Components Industries, Llc | Method of reducing residual contamination in singulated semiconductor die |
CN110634796A (zh) * | 2018-06-25 | 2019-12-31 | 半导体元件工业有限责任公司 | 用于处理电子管芯的方法及半导体晶圆和管芯的切单方法 |
US10607889B1 (en) * | 2018-09-19 | 2020-03-31 | Semiconductor Components Industries, Llc | Jet ablation die singulation systems and related methods |
US10818551B2 (en) | 2019-01-09 | 2020-10-27 | Semiconductor Components Industries, Llc | Plasma die singulation systems and related methods |
CN111640827B (zh) * | 2019-03-01 | 2021-03-12 | 山东浪潮华光光电子股份有限公司 | 一种GaAs基LED芯片的切割方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2836334B2 (ja) * | 1992-01-23 | 1998-12-14 | 三菱電機株式会社 | 高出力半導体装置の製造方法 |
US5268065A (en) * | 1992-12-21 | 1993-12-07 | Motorola, Inc. | Method for thinning a semiconductor wafer |
DE19618895A1 (de) | 1996-05-10 | 1997-11-13 | Itt Ind Gmbh Deutsche | Verfahren zum Bearbeiten von Seitenflächen elektronischer Elemente |
US5910687A (en) * | 1997-01-24 | 1999-06-08 | Chipscale, Inc. | Wafer fabrication of die-bottom contacts for electronic devices |
EP0860876A3 (de) * | 1997-02-21 | 1999-09-22 | DaimlerChrysler AG | Anordnung und Verfahren zur Herstellung von CSP-Gehäusen für elektrische Bauteile |
US5972781A (en) * | 1997-09-30 | 1999-10-26 | Siemens Aktiengesellschaft | Method for producing semiconductor chips |
JP2002093752A (ja) | 2000-09-14 | 2002-03-29 | Tokyo Electron Ltd | 半導体素子分離方法及び半導体素子分離装置 |
JP2002273824A (ja) * | 2001-03-16 | 2002-09-25 | Tomoegawa Paper Co Ltd | 接着剤付き銅箔積層体およびその作製方法 |
-
2002
- 2002-12-11 JP JP2002359051A patent/JP4013753B2/ja not_active Expired - Fee Related
-
2003
- 2003-12-10 US US10/732,677 patent/US7060531B2/en not_active Expired - Fee Related
- 2003-12-11 KR KR1020047019210A patent/KR100971760B1/ko not_active IP Right Cessation
- 2003-12-11 WO PCT/JP2003/015887 patent/WO2004053981A1/en active Application Filing
- 2003-12-11 AU AU2003295231A patent/AU2003295231A1/en not_active Abandoned
- 2003-12-11 EP EP03786235A patent/EP1570519B1/de not_active Expired - Lifetime
- 2003-12-11 AT AT03786235T patent/ATE489727T1/de not_active IP Right Cessation
- 2003-12-11 CN CNB2003801005002A patent/CN100356549C/zh not_active Expired - Fee Related
- 2003-12-11 DE DE60335137T patent/DE60335137D1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR100971760B1 (ko) | 2010-07-21 |
JP4013753B2 (ja) | 2007-11-28 |
CN1692493A (zh) | 2005-11-02 |
WO2004053981A1 (en) | 2004-06-24 |
CN100356549C (zh) | 2007-12-19 |
EP1570519A1 (de) | 2005-09-07 |
AU2003295231A1 (en) | 2004-06-30 |
KR20050084789A (ko) | 2005-08-29 |
ATE489727T1 (de) | 2010-12-15 |
EP1570519B1 (de) | 2010-11-24 |
JP2004193305A (ja) | 2004-07-08 |
US7060531B2 (en) | 2006-06-13 |
US20040121611A1 (en) | 2004-06-24 |
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