DE60208310T2 - Dreidimensionaler grosser Speicher mit wahlfreiem Zugriff - Google Patents

Dreidimensionaler grosser Speicher mit wahlfreiem Zugriff Download PDF

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Publication number
DE60208310T2
DE60208310T2 DE60208310T DE60208310T DE60208310T2 DE 60208310 T2 DE60208310 T2 DE 60208310T2 DE 60208310 T DE60208310 T DE 60208310T DE 60208310 T DE60208310 T DE 60208310T DE 60208310 T2 DE60208310 T2 DE 60208310T2
Authority
DE
Germany
Prior art keywords
memory
level
array
storage
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60208310T
Other languages
German (de)
English (en)
Other versions
DE60208310D1 (de
Inventor
Lung T. Tran
Thomas C. Anthony
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of DE60208310D1 publication Critical patent/DE60208310D1/de
Application granted granted Critical
Publication of DE60208310T2 publication Critical patent/DE60208310T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00—Three-dimensional [3D] integrated devices
    • H10D88/01—Manufacture or treatment
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
DE60208310T 2001-10-31 2002-10-25 Dreidimensionaler grosser Speicher mit wahlfreiem Zugriff Expired - Lifetime DE60208310T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/984,934 US6504742B1 (en) 2001-10-31 2001-10-31 3-D memory device for large storage capacity
US984934 2001-10-31

Publications (2)

Publication Number Publication Date
DE60208310D1 DE60208310D1 (de) 2006-02-02
DE60208310T2 true DE60208310T2 (de) 2006-07-27

Family

ID=25531039

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60208310T Expired - Lifetime DE60208310T2 (de) 2001-10-31 2002-10-25 Dreidimensionaler grosser Speicher mit wahlfreiem Zugriff

Country Status (6)

Country Link
US (1) US6504742B1 (enExample)
EP (1) EP1308958B1 (enExample)
JP (1) JP2003209222A (enExample)
KR (1) KR100895073B1 (enExample)
CN (1) CN1417861A (enExample)
DE (1) DE60208310T2 (enExample)

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EP1484698A4 (en) 2002-02-28 2013-06-12 Riken METHOD AND PROGRAM FOR IMPLEMENTING BORDER DATA IN AN IN CELL FORM
US6643159B2 (en) * 2002-04-02 2003-11-04 Hewlett-Packard Development Company, L.P. Cubic memory array
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US7312109B2 (en) * 2002-07-08 2007-12-25 Viciciv, Inc. Methods for fabricating fuse programmable three dimensional integrated circuits
US7129744B2 (en) * 2003-10-23 2006-10-31 Viciciv Technology Programmable interconnect structures
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US20040004251A1 (en) * 2002-07-08 2004-01-08 Madurawe Raminda U. Insulated-gate field-effect thin film transistors
US6856030B2 (en) * 2002-07-08 2005-02-15 Viciciv Technology Semiconductor latches and SRAM devices
US20040018711A1 (en) * 2002-07-08 2004-01-29 Madurawe Raminda U. Methods for fabricating three dimensional integrated circuits
US6992503B2 (en) * 2002-07-08 2006-01-31 Viciciv Technology Programmable devices with convertibility to customizable devices
US7064579B2 (en) * 2002-07-08 2006-06-20 Viciciv Technology Alterable application specific integrated circuit (ASIC)
US6998722B2 (en) * 2002-07-08 2006-02-14 Viciciv Technology Semiconductor latches and SRAM devices
US7112994B2 (en) * 2002-07-08 2006-09-26 Viciciv Technology Three dimensional integrated circuits
US6747478B2 (en) * 2002-07-08 2004-06-08 Viciciv Field programmable gate array with convertibility to application specific integrated circuit
US8643162B2 (en) * 2007-11-19 2014-02-04 Raminda Udaya Madurawe Pads and pin-outs in three dimensional integrated circuits
US7812458B2 (en) * 2007-11-19 2010-10-12 Tier Logic, Inc. Pad invariant FPGA and ASIC devices
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US7778062B2 (en) * 2003-03-18 2010-08-17 Kabushiki Kaisha Toshiba Resistance change memory device
WO2004084229A1 (en) * 2003-03-18 2004-09-30 Kabushiki Kaisha Toshiba Programmable resistance memory device
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JP4381743B2 (ja) 2003-07-16 2009-12-09 独立行政法人理化学研究所 境界表現データからボリュームデータを生成する方法及びそのプログラム
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KR100564611B1 (ko) * 2004-02-14 2006-03-29 삼성전자주식회사 하드 디스크 드라이브의 완충 구조체
US7112815B2 (en) 2004-02-25 2006-09-26 Micron Technology, Inc. Multi-layer memory arrays
US7489164B2 (en) * 2004-05-17 2009-02-10 Raminda Udaya Madurawe Multi-port memory devices
JP4662740B2 (ja) 2004-06-28 2011-03-30 日本電気株式会社 積層型半導体メモリ装置
US7589368B2 (en) * 2005-03-21 2009-09-15 Micronix International Co., Ltd. Three-dimensional memory devices
US7359279B2 (en) 2005-03-31 2008-04-15 Sandisk 3D Llc Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
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KR100855861B1 (ko) * 2005-12-30 2008-09-01 주식회사 하이닉스반도체 비휘발성 반도체 메모리 장치
US20070183189A1 (en) * 2006-02-08 2007-08-09 Thomas Nirschl Memory having nanotube transistor access device
US7486111B2 (en) * 2006-03-08 2009-02-03 Tier Logic, Inc. Programmable logic devices comprising time multiplexed programmable interconnect
US7345899B2 (en) * 2006-04-07 2008-03-18 Infineon Technologies Ag Memory having storage locations within a common volume of phase change material
JP2007322141A (ja) * 2006-05-30 2007-12-13 Yokogawa Electric Corp 半導体集積回路試験装置及び方法
JP2008140220A (ja) * 2006-12-04 2008-06-19 Nec Corp 半導体装置
US7692951B2 (en) * 2007-06-12 2010-04-06 Kabushiki Kaisha Toshiba Resistance change memory device with a variable resistance element formed of a first and a second composite compound
US8679977B2 (en) * 2007-07-25 2014-03-25 Micron Technology, Inc. Method and apparatus providing multi-planed array memory device
US7898893B2 (en) 2007-09-12 2011-03-01 Samsung Electronics Co., Ltd. Multi-layered memory devices
KR101330710B1 (ko) 2007-11-01 2013-11-19 삼성전자주식회사 플래시 메모리 장치
US7635988B2 (en) * 2007-11-19 2009-12-22 Tier Logic, Inc. Multi-port thin-film memory devices
US20090128189A1 (en) * 2007-11-19 2009-05-21 Raminda Udaya Madurawe Three dimensional programmable devices
US7573294B2 (en) * 2007-12-26 2009-08-11 Tier Logic, Inc. Programmable logic based latches and shift registers
US7573293B2 (en) * 2007-12-26 2009-08-11 Tier Logic, Inc. Programmable logic based latches and shift registers
US7795913B2 (en) * 2007-12-26 2010-09-14 Tier Logic Programmable latch based multiplier
US7602213B2 (en) * 2007-12-26 2009-10-13 Tier Logic, Inc. Using programmable latch to implement logic
US8230375B2 (en) 2008-09-14 2012-07-24 Raminda Udaya Madurawe Automated metal pattern generation for integrated circuits
KR20100038986A (ko) * 2008-10-07 2010-04-15 삼성전자주식회사 산화물 박막 트랜지스터를 포함하는 적층 메모리 장치
KR20100040580A (ko) 2008-10-10 2010-04-20 성균관대학교산학협력단 적층 메모리 소자
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US8159265B1 (en) 2010-11-16 2012-04-17 Raminda Udaya Madurawe Memory for metal configurable integrated circuits
US8159268B1 (en) 2010-11-16 2012-04-17 Raminda Udaya Madurawe Interconnect structures for metal configurable integrated circuits
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Also Published As

Publication number Publication date
US6504742B1 (en) 2003-01-07
KR100895073B1 (ko) 2009-04-27
DE60208310D1 (de) 2006-02-02
CN1417861A (zh) 2003-05-14
KR20030036028A (ko) 2003-05-09
EP1308958A3 (en) 2003-05-14
EP1308958A2 (en) 2003-05-07
EP1308958B1 (en) 2005-12-28
JP2003209222A (ja) 2003-07-25

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: KUHNEN & WACKER PATENT- UND RECHTSANWALTSBUERO, 85

8327 Change in the person/name/address of the patent owner

Owner name: SAMSUNG ELECTRONICS CO., LTD., SUWON, GYEONGGI, KR