DE69515927T2 - Breitbandige Halbleiterspeicheranordnungen - Google Patents

Breitbandige Halbleiterspeicheranordnungen

Info

Publication number
DE69515927T2
DE69515927T2 DE1995615927 DE69515927T DE69515927T2 DE 69515927 T2 DE69515927 T2 DE 69515927T2 DE 1995615927 DE1995615927 DE 1995615927 DE 69515927 T DE69515927 T DE 69515927T DE 69515927 T2 DE69515927 T2 DE 69515927T2
Authority
DE
Grant status
Grant
Patent type
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE1995615927
Other languages
English (en)
Other versions
DE69515927D1 (de )
Inventor
Dong-Il Seo
Se-Jin Jeong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
DE1995615927 1994-05-20 1995-05-15 Breitbandige Halbleiterspeicheranordnungen Expired - Lifetime DE69515927T2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR19940011050 1994-05-20

Publications (1)

Publication Number Publication Date
DE69515927T2 true DE69515927T2 (de) 2000-11-16

Family

ID=19383493

Family Applications (2)

Application Number Title Priority Date Filing Date
DE1995615927 Expired - Lifetime DE69515927D1 (de) 1994-05-20 1995-05-15 Breitbandige Halbleiterspeicheranordnungen
DE1995615927 Expired - Lifetime DE69515927T2 (de) 1994-05-20 1995-05-15 Breitbandige Halbleiterspeicheranordnungen

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE1995615927 Expired - Lifetime DE69515927D1 (de) 1994-05-20 1995-05-15 Breitbandige Halbleiterspeicheranordnungen

Country Status (6)

Country Link
US (3) US5537346A (de)
EP (1) EP0683493B1 (de)
JP (1) JP2786609B2 (de)
CN (1) CN1099117C (de)
DE (2) DE69515927D1 (de)
RU (1) RU2170955C2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10110624B4 (de) * 2001-03-06 2010-04-08 Qimonda Ag Integrierter Speicher mit mehreren Speicherbereichen

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6005820A (en) * 1993-12-07 1999-12-21 Texas Instruments Incorporated Field memories
JP3579205B2 (ja) 1996-08-06 2004-10-20 株式会社ルネサステクノロジ 半導体記憶装置、半導体装置、データ処理装置及びコンピュータシステム
JP3466034B2 (ja) * 1996-12-27 2003-11-10 富士通株式会社 半導体記憶装置
JPH10302471A (ja) * 1997-02-28 1998-11-13 Mitsubishi Electric Corp 半導体記憶装置
US6044481A (en) * 1997-05-09 2000-03-28 Artisan Components, Inc. Programmable universal test interface for testing memories with different test methodologies
US6072730A (en) * 1997-10-25 2000-06-06 Artisan Components, Inc. Low power differential signal transition techniques for use in memory devices
US6154386A (en) * 1998-06-16 2000-11-28 G-Link Technology Memory device having a wide data path
US6072737A (en) 1998-08-06 2000-06-06 Micron Technology, Inc. Method and apparatus for testing embedded DRAM
US6034900A (en) * 1998-09-02 2000-03-07 Micron Technology, Inc. Memory device having a relatively wide data bus
US6448631B2 (en) 1998-09-23 2002-09-10 Artisan Components, Inc. Cell architecture with local interconnect and method for making same
US6367059B1 (en) 1999-03-23 2002-04-02 Artisan Components, Inc. Carry chain standard cell with charge sharing reduction architecture
US6339541B1 (en) * 2000-06-16 2002-01-15 United Memories, Inc. Architecture for high speed memory circuit having a relatively large number of internal data lines
US6664634B2 (en) * 2001-03-15 2003-12-16 Micron Technology, Inc. Metal wiring pattern for memory devices
US7218564B2 (en) 2004-07-16 2007-05-15 Promos Technologies Inc. Dual equalization devices for long data line pairs
US8259509B2 (en) * 2008-08-18 2012-09-04 Elpida Memory, Inc. Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality
KR20100112490A (ko) * 2009-04-09 2010-10-19 삼성전자주식회사 데이터 라인 레이아웃
RU2453935C1 (ru) * 2010-10-26 2012-06-20 Валов Сергей Геннадьевич Способ снижения энергопотребления в n-мерной контекстно-адресуемой памяти
JP5684161B2 (ja) * 2012-01-26 2015-03-11 株式会社東芝 半導体装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01246091A (en) * 1988-03-29 1989-10-02 Amada Co Ltd Initial setting for arm length of swing type machine
JPH01278065A (en) * 1988-04-28 1989-11-08 Hitachi Ltd Semiconductor storage device
JPH0772991B2 (ja) * 1988-12-06 1995-08-02 三菱電機株式会社 半導体記憶装置
EP0454998B1 (de) * 1990-03-28 1995-11-08 Nec Corporation Halbleiterspeichereinrichtung
JPH0696582A (ja) * 1990-09-17 1994-04-08 Texas Instr Inc <Ti> メモリアレイアーキテクチャ
JPH0562461A (ja) * 1991-04-09 1993-03-12 Mitsubishi Electric Corp 半導体記憶装置
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
KR940003410B1 (ko) * 1991-08-01 1994-04-21 김광호 망사 구조의 전원선을 가지는 반도체 메모리 장치
EP0544247A3 (en) * 1991-11-27 1993-10-20 Texas Instruments Inc Memory architecture
JP2775552B2 (ja) * 1991-12-26 1998-07-16 三菱電機株式会社 半導体記憶装置
JP2938706B2 (ja) * 1992-04-27 1999-08-25 三菱電機株式会社 同期型半導体記憶装置
US5325336A (en) * 1992-09-10 1994-06-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having power line arranged in a meshed shape
US5457648A (en) * 1992-10-08 1995-10-10 Intel Corporation Random access memory with digital signals running over the small signal region of the array
DE69329788D1 (de) * 1992-10-14 2001-02-01 Sun Microsystems Inc Direktzugriffspeicherentwurf

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10110624B4 (de) * 2001-03-06 2010-04-08 Qimonda Ag Integrierter Speicher mit mehreren Speicherbereichen

Also Published As

Publication number Publication date Type
US5537346A (en) 1996-07-16 grant
RU2170955C2 (ru) 2001-07-20 grant
EP0683493B1 (de) 2000-03-29 grant
CN1099117C (zh) 2003-01-15 grant
DE69515927D1 (de) 2000-05-04 grant
JPH07320480A (ja) 1995-12-08 application
RU95107895A (ru) 1997-02-10 application
JP2786609B2 (ja) 1998-08-13 grant
CN1149187A (zh) 1997-05-07 application
EP0683493A2 (de) 1995-11-22 application
US5783480A (en) 1998-07-21 grant
EP0683493A3 (de) 1995-12-27 application
US5621679A (en) 1997-04-15 grant

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