DE602005023850D1 - Testeinrichtung und testverfahren - Google Patents

Testeinrichtung und testverfahren

Info

Publication number
DE602005023850D1
DE602005023850D1 DE602005023850T DE602005023850T DE602005023850D1 DE 602005023850 D1 DE602005023850 D1 DE 602005023850D1 DE 602005023850 T DE602005023850 T DE 602005023850T DE 602005023850 T DE602005023850 T DE 602005023850T DE 602005023850 D1 DE602005023850 D1 DE 602005023850D1
Authority
DE
Germany
Prior art keywords
phase
clock
generating
comparison result
reproduced clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602005023850T
Other languages
German (de)
English (en)
Inventor
Shusuke Kantake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of DE602005023850D1 publication Critical patent/DE602005023850D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31932—Comparators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2882—Testing timing characteristics
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Selective Calling Equipment (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
DE602005023850T 2004-03-26 2005-03-11 Testeinrichtung und testverfahren Expired - Lifetime DE602005023850D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004093310A JP4351941B2 (ja) 2004-03-26 2004-03-26 試験装置及び試験方法
PCT/JP2005/004370 WO2005093443A1 (ja) 2004-03-26 2005-03-11 試験装置及び試験方法

Publications (1)

Publication Number Publication Date
DE602005023850D1 true DE602005023850D1 (de) 2010-11-11

Family

ID=35056313

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005023850T Expired - Lifetime DE602005023850D1 (de) 2004-03-26 2005-03-11 Testeinrichtung und testverfahren

Country Status (9)

Country Link
US (1) US7549099B2 (https=)
EP (2) EP2233936A1 (https=)
JP (1) JP4351941B2 (https=)
KR (1) KR20070027539A (https=)
CN (1) CN1934455B (https=)
AT (1) ATE483169T1 (https=)
DE (1) DE602005023850D1 (https=)
TW (1) TWI353454B (https=)
WO (1) WO2005093443A1 (https=)

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US7394277B2 (en) * 2006-04-20 2008-07-01 Advantest Corporation Testing apparatus, testing method, jitter filtering circuit, and jitter filtering method
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JP4944771B2 (ja) * 2006-05-01 2012-06-06 株式会社アドバンテスト 試験装置、回路および電子デバイス
JP4792340B2 (ja) * 2006-07-11 2011-10-12 株式会社アドバンテスト 試験装置および試験方法
US7574633B2 (en) 2006-07-12 2009-08-11 Advantest Corporation Test apparatus, adjustment method and recording medium
JP4806599B2 (ja) * 2006-07-20 2011-11-02 株式会社アドバンテスト 電気回路および試験装置
WO2008120389A1 (ja) * 2007-03-29 2008-10-09 Fujitsu Limited メモリテスト回路、半導体集積回路およびメモリテスト方法
DE112007003471T5 (de) 2007-04-25 2010-03-18 Advantest Corp. Prüfgerät
JP5113846B2 (ja) * 2007-08-16 2013-01-09 株式会社アドバンテスト 取得装置、試験装置および製造方法
JPWO2009031404A1 (ja) 2007-09-04 2010-12-09 株式会社アドバンテスト 伝送回路、送信器、受信器、および、試験装置
JP4967942B2 (ja) * 2007-09-12 2012-07-04 横河電機株式会社 半導体試験装置
US8111082B2 (en) 2008-06-09 2012-02-07 Advantest Corporation Test apparatus
JPWO2009150819A1 (ja) 2008-06-10 2011-11-10 株式会社アドバンテスト 試験モジュール、試験装置および試験方法
KR100942953B1 (ko) * 2008-06-30 2010-02-17 주식회사 하이닉스반도체 데이터 전달 회로 및 그를 포함하는 반도체 메모리 장치
CN102317803A (zh) * 2008-07-09 2012-01-11 爱德万测试株式会社 测试装置、测试方法和移相器
WO2010004755A1 (ja) * 2008-07-09 2010-01-14 株式会社アドバンテスト 試験装置、及び試験方法
JP5124023B2 (ja) 2008-08-01 2013-01-23 株式会社アドバンテスト 試験装置
CN102124357A (zh) * 2008-08-19 2011-07-13 爱德万测试株式会社 测试装置及测试方法
WO2010026642A1 (ja) 2008-09-04 2010-03-11 株式会社アドバンテスト 試験装置、送信装置、受信装置、試験方法、送信方法、および受信方法
US8819474B2 (en) * 2009-04-03 2014-08-26 Intel Corporation Active training of memory command timing
WO2012007986A1 (ja) * 2010-07-12 2012-01-19 株式会社アドバンテスト 測定回路および試験装置
CN102854451A (zh) * 2011-06-29 2013-01-02 鸿富锦精密工业（深圳）有限公司 印刷电路板的信号群延迟分析系统及方法
CN103116124B (zh) * 2011-11-17 2016-05-18 国民技术股份有限公司 可自校准内部晶振的芯片、晶振校准测试系统及校准方法
CN103280241B (zh) * 2013-04-22 2018-05-01 北京大学深圳研究生院 存储器的测试电路及方法
CN103235254B (zh) * 2013-04-25 2016-03-02 杭州和利时自动化有限公司 一种可编程逻辑器件的检测方法和检测系统
CN105807134A (zh) * 2014-12-31 2016-07-27 无锡华润矽科微电子有限公司 频率测试仪及频率测试系统
CN104836576B (zh) * 2015-04-30 2018-11-02 华南理工大学 一种改进高频畸变波形相位检测的锁相环
CN107703437B (zh) * 2017-09-14 2019-08-13 西安交通大学 一种基于半频静电激振的高频体模态谐振器测试方法
US10719568B2 (en) * 2017-11-28 2020-07-21 International Business Machines Corporation Fixing embedded richtext links in copied related assets
CN108614206B (zh) * 2018-04-03 2020-08-04 上海华力微电子有限公司 一种芯片测试装置、测试方法及测试板
US11102596B2 (en) 2019-11-19 2021-08-24 Roku, Inc. In-sync digital waveform comparison to determine pass/fail results of a device under test (DUT)
KR102278648B1 (ko) * 2020-02-13 2021-07-16 포스필 주식회사 피시험 디바이스를 테스트하기 위한 방법 및 장치
CN112965910B (zh) * 2021-03-19 2024-06-21 携程旅游信息技术（上海）有限公司 自动化回归测试方法、装置、电子设备、存储介质
CN115327191B (zh) * 2021-05-11 2025-05-06 圣邦微电子（北京）股份有限公司 一种改善芯片测试设备测试精度的电路及方法
USD1037855S1 (en) 2021-06-25 2024-08-06 Diageo North America, Inc. Bottle
USD1023769S1 (en) 2021-07-01 2024-04-23 Diageo North America, Inc. Surface ornamentation for a bottle
USD1051726S1 (en) 2021-07-28 2024-11-19 Diageo North America, Inc. Bottle
JP7712138B2 (ja) * 2021-08-04 2025-07-23 株式会社アドバンテスト 装置
US12207058B2 (en) * 2021-12-29 2025-01-21 The Nielsen Co. (US) LLC Methods, systems, apparatus, and articles of manufacture to determine performance of audience measurement meters

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JP3698657B2 (ja) * 2001-06-12 2005-09-21 シャープ株式会社 ゲーティッドクロック生成回路及び回路修正方法
JP2003023353A (ja) * 2001-07-09 2003-01-24 Matsushita Electric Ind Co Ltd Ｐｌｌ回路
JP2003098233A (ja) * 2001-09-27 2003-04-03 Sony Corp 動作時間測定回路
JP4048903B2 (ja) * 2001-11-28 2008-02-20 ヤマハ株式会社 テスト回路
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JP4002471B2 (ja) * 2002-05-30 2007-10-31 エルピーダメモリ株式会社 試験装置
JP4291596B2 (ja) * 2003-02-26 2009-07-08 株式会社ルネサステクノロジ 半導体集積回路の試験装置およびそれを用いた半導体集積回路の製造方法
US6794913B1 (en) * 2003-05-29 2004-09-21 Motorola, Inc. Delay locked loop with digital to phase converter compensation

Also Published As

Publication number Publication date
KR20070027539A (ko) 2007-03-09
TW200532227A (en) 2005-10-01
ATE483169T1 (de) 2010-10-15
EP1742074B1 (en) 2010-09-29
US20070006031A1 (en) 2007-01-04
CN1934455B (zh) 2010-05-05
TWI353454B (en) 2011-12-01
CN1934455A (zh) 2007-03-21
JP2005285160A (ja) 2005-10-13
EP1742074A4 (en) 2009-07-01
EP2233936A1 (en) 2010-09-29
EP1742074A1 (en) 2007-01-10
US7549099B2 (en) 2009-06-16
JP4351941B2 (ja) 2009-10-28
WO2005093443A1 (ja) 2005-10-06

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