WO2010013464A1 - 試験装置 - Google Patents

試験装置 Download PDF

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Publication number
WO2010013464A1
WO2010013464A1 PCT/JP2009/003590 JP2009003590W WO2010013464A1 WO 2010013464 A1 WO2010013464 A1 WO 2010013464A1 JP 2009003590 W JP2009003590 W JP 2009003590W WO 2010013464 A1 WO2010013464 A1 WO 2010013464A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
strobe signal
outputs
delay element
strb1c
Prior art date
Application number
PCT/JP2009/003590
Other languages
English (en)
French (fr)
Inventor
上松知宏
Original Assignee
株式会社アドバンテスト
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社アドバンテスト filed Critical 株式会社アドバンテスト
Priority to CN2009801283429A priority Critical patent/CN102099700A/zh
Priority to JP2010522621A priority patent/JP5124023B2/ja
Priority to US13/055,982 priority patent/US8542003B2/en
Publication of WO2010013464A1 publication Critical patent/WO2010013464A1/ja

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)

Abstract

　第１タイミングコンパレータＴＣＰ１は、データ信号ＤＱを、第１ストローブ信号ＳＴＲＢ１ａのエッジに応じたタイミングでラッチする。第１遅延素子Ｄ１は、第１ストローブ信号ＳＴＲＢ１ａを遅延させ、第１遅延ストローブ信号ＳＴＲＢ１ｂを出力する。第１クロック再生部ＣＤＲ１は、第１遅延ストローブ信号ＳＴＲＢ１ｂとクロック信号ＳＳＣＬＫ’の位相を比較し、両者が一致するように位相が調節される第１基準ストローブ信号ＳＴＲＢ１ｃを出力する。第３遅延素子Ｄ３は、第１基準ストローブ信号ＳＴＲＢ１ｃを遅延させ、第１ストローブ信号ＳＴＲＢ１として出力する。第３遅延素子Ｄ３には、データ信号ＤＱとクロック信号ＳＳＣＬＫのスキュー量に応じた遅延が設定される。
PCT/JP2009/003590 2008-08-01 2009-07-29 試験装置 WO2010013464A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN2009801283429A CN102099700A (zh) 2008-08-01 2009-07-29 测试装置
JP2010522621A JP5124023B2 (ja) 2008-08-01 2009-07-29 試験装置
US13/055,982 US8542003B2 (en) 2008-08-01 2009-07-29 Test apparatus to test a data signal and a clock signal output from a device under test

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008199987 2008-08-01
JP2008-199987 2008-08-01

Publications (1)

Publication Number Publication Date
WO2010013464A1 true WO2010013464A1 (ja) 2010-02-04

Family

ID=41610178

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2009/003590 WO2010013464A1 (ja) 2008-08-01 2009-07-29 試験装置

Country Status (4)

Country Link
US (1) US8542003B2 (ja)
JP (1) JP5124023B2 (ja)
CN (1) CN102099700A (ja)
WO (1) WO2010013464A1 (ja)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9246666B2 (en) * 2014-03-27 2016-01-26 Intel Corporation Skew tolerant clock recovery architecture
US9454468B2 (en) * 2014-06-27 2016-09-27 Wipro Limited Method and system for testing software
US10236074B1 (en) * 2017-05-12 2019-03-19 Xilinx, Inc. Circuits for and methods of making measurements in a testing arrangement having a plurality of devices under test
US10347307B2 (en) * 2017-06-29 2019-07-09 SK Hynix Inc. Skew control circuit and interface circuit including the same
KR102512985B1 (ko) * 2018-06-12 2023-03-22 삼성전자주식회사 반도체 장치를 위한 테스트 장치 및 반도체 장치의 제조 방법
KR20200106732A (ko) * 2019-03-05 2020-09-15 에스케이하이닉스 주식회사 반도체장치
CN113450866B (zh) 2020-03-27 2022-04-12 长鑫存储技术有限公司 存储器测试方法
US11514958B2 (en) * 2020-08-10 2022-11-29 Teradyne, Inc. Apparatus and method for operating source synchronous devices

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1653650A1 (en) * 2004-10-27 2006-05-03 Agilent Technologies Inc Source synchronous sampling
JP2007048386A (ja) * 2005-08-10 2007-02-22 Advantest Corp 試験装置および試験方法
WO2007043480A1 (ja) * 2005-10-11 2007-04-19 Advantest Corporation 試験装置、プログラム、及び記録媒体
WO2007129386A1 (ja) * 2006-05-01 2007-11-15 Advantest Corporation 試験装置および試験方法
US20070282555A1 (en) * 2006-04-21 2007-12-06 Altera Corporation Read-Side Calibration for Data Interface
JP2009068949A (ja) * 2007-09-12 2009-04-02 Yokogawa Electric Corp 半導体試験装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7263646B2 (en) * 2000-12-29 2007-08-28 Intel Corporation Method and apparatus for skew compensation
JP4002811B2 (ja) * 2002-10-04 2007-11-07 株式会社アドバンテスト マルチストローブ生成装置、試験装置、及び調整方法
US7036053B2 (en) * 2002-12-19 2006-04-25 Intel Corporation Two dimensional data eye centering for source synchronous data transfers
EP1696564A1 (en) * 2003-11-20 2006-08-30 Advantest Corporation Variable delay circuit
JP4351941B2 (ja) 2004-03-26 2009-10-28 株式会社アドバンテスト 試験装置及び試験方法
CN1996760A (zh) * 2006-01-06 2007-07-11 矽统科技股份有限公司 应用于时钟源同步机制中的利用相位域和时域混合控制时钟相位校准的装置及其校准方法
US7900129B2 (en) * 2007-01-29 2011-03-01 Via Technologies, Inc. Encoded mechanism for source synchronous strobe lockout

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1653650A1 (en) * 2004-10-27 2006-05-03 Agilent Technologies Inc Source synchronous sampling
JP2007048386A (ja) * 2005-08-10 2007-02-22 Advantest Corp 試験装置および試験方法
WO2007043480A1 (ja) * 2005-10-11 2007-04-19 Advantest Corporation 試験装置、プログラム、及び記録媒体
US20070282555A1 (en) * 2006-04-21 2007-12-06 Altera Corporation Read-Side Calibration for Data Interface
WO2007129386A1 (ja) * 2006-05-01 2007-11-15 Advantest Corporation 試験装置および試験方法
JP2009068949A (ja) * 2007-09-12 2009-04-02 Yokogawa Electric Corp 半導体試験装置

Also Published As

Publication number Publication date
JPWO2010013464A1 (ja) 2012-01-05
CN102099700A (zh) 2011-06-15
US20110121814A1 (en) 2011-05-26
US8542003B2 (en) 2013-09-24
JP5124023B2 (ja) 2013-01-23

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