WO2007099579A9 - Ramマクロ、そのタイミング生成回路 - Google Patents
Ramマクロ、そのタイミング生成回路 Download PDFInfo
- Publication number
- WO2007099579A9 WO2007099579A9 PCT/JP2006/303656 JP2006303656W WO2007099579A9 WO 2007099579 A9 WO2007099579 A9 WO 2007099579A9 JP 2006303656 W JP2006303656 W JP 2006303656W WO 2007099579 A9 WO2007099579 A9 WO 2007099579A9
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- clock
- test
- generating circuit
- timing generating
- circuit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12015—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising clock generation or timing circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Dram (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Static Random-Access Memory (AREA)
Abstract
タイミング生成回路13は、外部からの入力クロックCLKを基に、制御クロック(1)、テストクロック(2)を生成して、テスト回路14に出力する。制御クロック(1)は、クロックCLKを基準として、所定量、位相を遅らせた信号となるが、この所定量は外部からのテスト信号によって設定・変更できる。テストクロック(2)はほぼクロックCLKの反転信号となる。テスト回路14は、上記クロック(1)、(2)のどちらかを基に、各種制御信号(4)を生成して制御回路12に分配する。テスト回路14において上記クロック(1)、(2)のどちらかを選択するのかは、外部からのテスト信号によって設定できる。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008502566A JP4957719B2 (ja) | 2006-02-28 | 2006-02-28 | Ramマクロ、そのタイミング生成回路 |
DE602006015236T DE602006015236D1 (de) | 2006-02-28 | 2006-02-28 | Ram-makro und timing-erzeugungsschaltung dafür |
PCT/JP2006/303656 WO2007099579A1 (ja) | 2006-02-28 | 2006-02-28 | Ramマクロ、そのタイミング生成回路 |
EP06714793A EP1990805B1 (en) | 2006-02-28 | 2006-02-28 | Ram macro and timing generating circuit for same |
US12/198,373 US8000157B2 (en) | 2006-02-28 | 2008-08-26 | RAM macro and timing generating circuit thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2006/303656 WO2007099579A1 (ja) | 2006-02-28 | 2006-02-28 | Ramマクロ、そのタイミング生成回路 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US12/198,373 Continuation US8000157B2 (en) | 2006-02-28 | 2008-08-26 | RAM macro and timing generating circuit thereof |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2007099579A1 WO2007099579A1 (ja) | 2007-09-07 |
WO2007099579A8 WO2007099579A8 (ja) | 2008-09-18 |
WO2007099579A9 true WO2007099579A9 (ja) | 2009-05-14 |
Family
ID=38458702
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2006/303656 WO2007099579A1 (ja) | 2006-02-28 | 2006-02-28 | Ramマクロ、そのタイミング生成回路 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8000157B2 (ja) |
EP (1) | EP1990805B1 (ja) |
JP (1) | JP4957719B2 (ja) |
DE (1) | DE602006015236D1 (ja) |
WO (1) | WO2007099579A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5060794B2 (ja) * | 2007-02-06 | 2012-10-31 | 株式会社リコー | 半導体記憶装置 |
ATE541310T1 (de) | 2007-10-09 | 2012-01-15 | Fujitsu Ltd | Integriertes halbleiterschaltungsbauelement |
US7668037B2 (en) * | 2007-11-06 | 2010-02-23 | International Business Machines Corporation | Storage array including a local clock buffer with programmable timing |
US8332552B2 (en) * | 2008-11-13 | 2012-12-11 | International Business Machines Corporation | Supporting multiple high bandwidth I/O controllers on a single chip |
US8051228B2 (en) * | 2008-11-13 | 2011-11-01 | International Business Machines Corporation | Physical interface macros (PHYS) supporting heterogeneous electrical properties |
JP5539916B2 (ja) * | 2011-03-04 | 2014-07-02 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR102392903B1 (ko) * | 2017-10-23 | 2022-05-03 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그의 동작 방법 |
US10983725B2 (en) * | 2018-03-01 | 2021-04-20 | Synopsys, Inc. | Memory array architectures for memory queues |
TWI744157B (zh) * | 2020-12-31 | 2021-10-21 | 瑞昱半導體股份有限公司 | 內嵌式記憶體系統與記憶體測試方法 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4608669A (en) * | 1984-05-18 | 1986-08-26 | International Business Machines Corporation | Self contained array timing |
US4916670A (en) * | 1988-02-02 | 1990-04-10 | Fujitsu Limited | Semiconductor memory device having function of generating write signal internally |
JP2509275B2 (ja) * | 1988-02-02 | 1996-06-19 | 富士通株式会社 | 半導体メモリ装置 |
JPH0752600B2 (ja) * | 1988-09-27 | 1995-06-05 | 日本電気株式会社 | 半導体メモリ素子 |
JPH03230395A (ja) * | 1990-02-02 | 1991-10-14 | Hitachi Ltd | スタティック型ram |
JPH04134695A (ja) * | 1990-09-25 | 1992-05-08 | Nec Corp | 半導体メモリ |
JPH0729375A (ja) * | 1993-07-14 | 1995-01-31 | Seiko Epson Corp | 半導体記憶装置 |
JP3591887B2 (ja) * | 1994-09-12 | 2004-11-24 | 富士通株式会社 | 半導体記憶装置 |
US5764592A (en) * | 1996-12-21 | 1998-06-09 | Sgs-Thomson Microelectronics, Inc. | External write pulse control method and structure |
JPH10283777A (ja) * | 1997-04-04 | 1998-10-23 | Mitsubishi Electric Corp | Sdramコアと論理回路を単一チップ上に混載した半導体集積回路装置およびsdramコアのテスト方法 |
JPH11144497A (ja) * | 1997-11-13 | 1999-05-28 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP4301680B2 (ja) * | 2000-02-29 | 2009-07-22 | 株式会社ルネサステクノロジ | 半導体集積回路装置 |
JP2001307499A (ja) * | 2000-04-24 | 2001-11-02 | Nec Corp | 半導体記憶装置 |
JP2002042466A (ja) * | 2000-07-21 | 2002-02-08 | Mitsubishi Electric Corp | 半導体装置および半導体記憶装置 |
US6643807B1 (en) * | 2000-08-01 | 2003-11-04 | International Business Machines Corporation | Array-built-in-self-test (ABIST) for efficient, fast, bitmapping of large embedded arrays in manufacturing test |
US6829728B2 (en) * | 2000-11-13 | 2004-12-07 | Wu-Tung Cheng | Full-speed BIST controller for testing embedded synchronous memories |
JP2002298580A (ja) * | 2001-03-28 | 2002-10-11 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP2004022014A (ja) * | 2002-06-13 | 2004-01-22 | Nec Micro Systems Ltd | 半導体装置およびそのテスト方法 |
JP2004158144A (ja) * | 2002-11-07 | 2004-06-03 | Renesas Technology Corp | 半導体集積回路 |
JP2005141817A (ja) * | 2003-11-05 | 2005-06-02 | Toshiba Corp | 半導体集積回路 |
KR100583152B1 (ko) * | 2004-02-19 | 2006-05-23 | 주식회사 하이닉스반도체 | 데이터 억세스타임 측정모드를 갖는 반도체 메모리 소자 |
-
2006
- 2006-02-28 DE DE602006015236T patent/DE602006015236D1/de active Active
- 2006-02-28 WO PCT/JP2006/303656 patent/WO2007099579A1/ja active Application Filing
- 2006-02-28 EP EP06714793A patent/EP1990805B1/en not_active Expired - Fee Related
- 2006-02-28 JP JP2008502566A patent/JP4957719B2/ja not_active Expired - Fee Related
-
2008
- 2008-08-26 US US12/198,373 patent/US8000157B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1990805A4 (en) | 2009-06-10 |
US8000157B2 (en) | 2011-08-16 |
EP1990805B1 (en) | 2010-06-30 |
JPWO2007099579A1 (ja) | 2009-07-16 |
EP1990805A1 (en) | 2008-11-12 |
WO2007099579A1 (ja) | 2007-09-07 |
DE602006015236D1 (de) | 2010-08-12 |
US20090059713A1 (en) | 2009-03-05 |
JP4957719B2 (ja) | 2012-06-20 |
WO2007099579A8 (ja) | 2008-09-18 |
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