DE602004004483D1 - Verfahren zur Herstellung einer Doppeldamaszen-Metallverbindung - Google Patents

Verfahren zur Herstellung einer Doppeldamaszen-Metallverbindung

Info

Publication number
DE602004004483D1
DE602004004483D1 DE602004004483T DE602004004483T DE602004004483D1 DE 602004004483 D1 DE602004004483 D1 DE 602004004483D1 DE 602004004483 T DE602004004483 T DE 602004004483T DE 602004004483 T DE602004004483 T DE 602004004483T DE 602004004483 D1 DE602004004483 D1 DE 602004004483D1
Authority
DE
Germany
Prior art keywords
producing
metal compound
dual damascene
damascene metal
dual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004004483T
Other languages
English (en)
Other versions
DE602004004483T2 (de
Inventor
Jae-Hak Kim
Young-Joon Moon
Kyoung-Woo Lee
Jeong-Wook Hwang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE602004004483D1 publication Critical patent/DE602004004483D1/de
Application granted granted Critical
Publication of DE602004004483T2 publication Critical patent/DE602004004483T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE602004004483T 2003-12-03 2004-11-25 Verfahren zur Bildung einer Doppeldamaszener-Metallzwischenverbindung Active DE602004004483T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020030087351A KR100583957B1 (ko) 2003-12-03 2003-12-03 희생금속산화막을 채택하여 이중다마신 금속배선을형성하는 방법
KR2003087351 2003-12-03

Publications (2)

Publication Number Publication Date
DE602004004483D1 true DE602004004483D1 (de) 2007-03-15
DE602004004483T2 DE602004004483T2 (de) 2007-05-24

Family

ID=34464802

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004004483T Active DE602004004483T2 (de) 2003-12-03 2004-11-25 Verfahren zur Bildung einer Doppeldamaszener-Metallzwischenverbindung

Country Status (5)

Country Link
US (1) US7064059B2 (de)
EP (1) EP1538665B1 (de)
KR (1) KR100583957B1 (de)
CN (1) CN1306590C (de)
DE (1) DE602004004483T2 (de)

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KR100632658B1 (ko) * 2004-12-29 2006-10-12 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성방법
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US20060183055A1 (en) * 2005-02-15 2006-08-17 O'neill Mark L Method for defining a feature on a substrate
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US20060286792A1 (en) * 2005-06-20 2006-12-21 Taiwan Semiconductor Manufacturing Co., Ltd. Dual damascene process
US7547598B2 (en) * 2006-01-09 2009-06-16 Hynix Semiconductor Inc. Method for fabricating capacitor in semiconductor device
US7300868B2 (en) * 2006-03-30 2007-11-27 Sony Corporation Damascene interconnection having porous low k layer with a hard mask reduced in thickness
US7456099B2 (en) * 2006-05-25 2008-11-25 International Business Machines Corporation Method of forming a structure for reducing lateral fringe capacitance in semiconductor devices
US20070290347A1 (en) * 2006-06-19 2007-12-20 Texas Instruments Incorporated Semiconductive device having resist poison aluminum oxide barrier and method of manufacture
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JP5268084B2 (ja) * 2006-12-22 2013-08-21 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7906426B2 (en) * 2007-04-23 2011-03-15 Globalfoundries Singapore Pte. Ltd. Method of controlled low-k via etch for Cu interconnections
US7960290B2 (en) * 2007-05-02 2011-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a semiconductor device
KR100871768B1 (ko) * 2007-05-18 2008-12-05 주식회사 동부하이텍 반도체 소자 및 ｂｏａｃ/ｃｏａ 제조 방법
KR100843716B1 (ko) * 2007-05-18 2008-07-04 삼성전자주식회사 자기 정렬된 콘택플러그를 갖는 반도체소자의 제조방법 및관련된 소자
JP2009164175A (ja) * 2007-12-28 2009-07-23 Toshiba Corp 半導体装置の製造方法
US8293634B2 (en) * 2008-08-07 2012-10-23 International Business Machines Corporation Structures and methods for improving solder bump connections in semiconductor devices
US8357617B2 (en) 2008-08-22 2013-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of patterning a metal gate of semiconductor device
CN101794071A (zh) * 2008-09-22 2010-08-04 台湾积体电路制造股份有限公司 半导体装置的制造方法
JP5407340B2 (ja) * 2009-01-07 2014-02-05 富士通セミコンダクター株式会社 配線の形成方法
SG176144A1 (en) * 2009-06-25 2011-12-29 Lam Res Ag Method for treating a semiconductor wafer
CN101996927B (zh) * 2009-08-14 2012-10-03 中芯国际集成电路制造(上海)有限公司 多层互连结构及其形成方法
CN102386088B (zh) * 2010-09-03 2014-06-25 中芯国际集成电路制造(上海)有限公司 用于去除半导体器件结构上的光致抗蚀剂层的方法
CN102420169A (zh) * 2011-05-13 2012-04-18 上海华力微电子有限公司 通孔填充牺牲材料的超厚顶层金属双大马士革工艺
CN102983098A (zh) * 2011-09-07 2013-03-20 中国科学院微电子研究所 后栅工艺中电极和连线的制造方法
CN102437101B (zh) * 2011-09-09 2015-06-24 上海华力微电子有限公司 一种改进的硬质掩膜与多孔低介电常数值材料的集成方法
KR20140089650A (ko) 2013-01-03 2014-07-16 삼성디스플레이 주식회사 액정 표시 장치 및 그 제조 방법
KR102145825B1 (ko) 2014-07-28 2020-08-19 삼성전자 주식회사 반도체 소자 및 그 제조 방법
KR102201092B1 (ko) * 2014-09-16 2021-01-11 삼성전자주식회사 반도체 장치 제조 방법
KR102394042B1 (ko) 2016-03-11 2022-05-03 인프리아 코포레이션 사전패터닝된 리소그래피 템플레이트, 상기 템플레이트를 이용한 방사선 패터닝에 기초한 방법 및 상기 템플레이트를 형성하기 위한 방법
CN106887388A (zh) * 2017-02-14 2017-06-23 上海华虹宏力半导体制造有限公司 金属结构光刻蚀刻方法以及金属结构光刻蚀刻结构
CN108878363B (zh) * 2017-05-12 2021-07-13 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN109755126B (zh) * 2017-11-07 2021-02-12 中芯国际集成电路制造(上海)有限公司 半导体器件的制造方法
JP2021068718A (ja) * 2018-02-15 2021-04-30 東京エレクトロン株式会社 基板処理システム、基板処理装置及び基板処理方法
US11171052B2 (en) 2019-04-29 2021-11-09 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming interconnect structures with selectively deposited pillars and structures formed thereby
US11024533B2 (en) * 2019-05-16 2021-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of forming interconnect structures using via holes filled with dielectric film
US11069610B2 (en) 2019-10-15 2021-07-20 Micron Technology, Inc. Methods for forming microelectronic devices with self-aligned interconnects, and related devices and systems
KR20230005970A (ko) 2020-05-06 2023-01-10 인프리아 코포레이션 중간 고정 단계가 있는 유기금속 광패턴가능 층을 사용한 다중 패터닝

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Also Published As

Publication number Publication date
US7064059B2 (en) 2006-06-20
EP1538665B1 (de) 2007-01-24
CN1306590C (zh) 2007-03-21
CN1624897A (zh) 2005-06-08
KR20050054064A (ko) 2005-06-10
KR100583957B1 (ko) 2006-05-26
EP1538665A1 (de) 2005-06-08
DE602004004483T2 (de) 2007-05-24
US20050124149A1 (en) 2005-06-09

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