CN101185160A - 固化氢倍半硅氧烷和在纳米级沟槽内致密化的方法 - Google Patents
固化氢倍半硅氧烷和在纳米级沟槽内致密化的方法 Download PDFInfo
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- H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
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Abstract
通过下述步骤填充在半导体基底内的沟槽:(i)在半导体基底上和在沟槽内分配成膜材料;(ii)在第一低温下,在氧化剂存在下固化分配的成膜材料第一预定的时间段;(iii)在第二低温下,在氧化剂存在下固化分配的成膜材料第二预定的时间段;(iv)在第三高温下,在氧化剂存在下固化分配的成膜材料第三预定的时间段;和(v)在半导体基底内形成填充的氧化物沟槽。该成膜材料是氢倍半硅氧烷。
Description
相关申请的交叉参考
[0001]无
发明领域
[0002]在高长径比的纳米级沟槽内固化氢倍半硅氧烷(HSQ)的方法。高长径比一般是指又窄又深的沟槽。相对于沟槽深度,沟槽宽度越窄,则长径比越高。固化技术牵涉在三个不同温度范围下在诸如水蒸汽和/或一氧化二氮之类氧化剂等存在下进行的三阶段工序。
发明背景
[0003]集成电路技术在半导体基底上使用窄的沟槽,以隔离诸如预金属电介质(PMD)之类的电路和浅沟槽隔离(STI)。绝缘材料沉积在沟槽内,形成绝缘层,并使形貌平面化。化学气相沉积(CVD)和旋涂玻璃沉积(SOD)是典型地使用的在半导体基底上填充沟槽技术,以便形成电介质层,例如二氧化硅(SiO2)和二氧化硅基层。
[0004]典型的CVD方法牵涉将基底置于工艺过程气体引入其内并加热的反应器腔室内。这将诱导一系列的化学反应,所述化学反应将导致在基底上沉积所需的层。可使用CVD方法,制备由硅烷(SiH4)或四乙氧基硅烷Si(OC2H5)制造的二氧化硅膜。已知各类CVD方法,例如大气压CVD、低压CVD或等离子体加强的CVD。然而,CVD方法的缺点可能是,当沟槽的深度尺寸接近亚微米级时,难以充分地填充沟槽。因此CVD技术不适合于本发明具有高长径比的纳米级沟槽填充。
[0005]在典型的SOD方法中,将含成膜材料例如HSQ树脂的溶液沉积在基底上,并利用某些旋转参数旋转铺涂,形成均匀的薄膜,溶液的可旋涂性直接影响薄膜的质量和性能。在成膜材料沉积于基底上之后,固化成膜材料。SOD是本发明方法的技术。
发明简述
[0006]本发明涉及填充半导体基底内沟槽的方法。通过下述步骤来填充沟槽:
在半导体基底上和在沟槽内分配成膜材料;
在第一低温下,在氧化剂存在下固化分配的成膜材料第一预定的时间段;
在第二低温下,在氧化剂存在下固化分配的成膜材料第二预定的时间段;
在第三高温下,在氧化剂存在下固化分配的成膜材料第三预定的时间段;和
在半导体基底内形成填充的氧化物沟槽。
[0007]所述成膜材料是氢倍半硅氧烷的溶液,和氧化剂可以是一氧化二氮、氧化一氮、水蒸汽和类似物。通过旋涂方法,将氢倍半硅氧烷成膜材料沉积在半导体基底上和沟槽内。第一低温是20-25℃至100℃,第二低温是100-400℃,和第三高温是800-900℃。视需要,可在400-800℃的温度下,在一氧化二氮存在下,致密化在半导体基底内的填充的氧化物沟槽。第一、第二和第三预定的时间段以及致密化的时间各自为30-60分钟。根据以下详细说明的考虑,本发明的这些和其他特征将变得显而易见。
附图简述
[0008]图1是在固化并湿法蚀刻在构图的晶片上制造的膜之后,该膜的扫描电子显微(SEM)图像的截面。
发明详述
氢倍半硅氧烷
[0009]此处所使用的氢倍半硅氧烷是先驱体(preceramic)含硅树脂,更特别地,含有通式HSi(OH)x(OR)yOz/2的单元的氢硅氧烷树脂。R独立地为有机基团,当该有机基团通过氧原子键合到硅上时,将形成可水解的取代基。合适的R基包括:烷基,例如甲基、乙基、丙基和丁基;芳基,例如苯基;和链烯基,例如烯丙基或乙烯基。X的数值为0-2;y为0-2;z为1-3;和x+y+z之和为3。
[0010]这些树脂可以是(i)充分缩合的氢倍半硅氧烷树脂(HSiO3/2)n;(ii)仅仅部分水解的,即含有一些≡SiOR的树脂;和/或部分缩合的,即含有一些≡SiOH的树脂。另外,该树脂可含有小于约10%或者不具有氢原子或者具有两个氢原子的硅原子,或者氧空位以及≡Si-Si≡键可在其形成或处理过程中出现。
[0011]氢倍半硅氧烷树脂是通常符合以下描述结构的梯形或笼形聚合物。
[0012]典型地,n的数值为大于或等于4。作为例举,当n为4时,以下描述了倍半硅氧烷立方八聚体的化学键布局:
[0013]当该序列延长,即n为大于或等于5时,形成无限高分子量的两股聚硅氧烷,所述聚硅氧烷在其延长的结构内含有规则和反复的交联。
[0014]在美国专利3615272(1971年10月26日)公开了氢倍半硅氧烷树脂及其制备方法,在此通过参考将其引入。根据′272专利中的方法,可通过在苯磺酸水合物介质内水解三氯硅烷(HSiCl3),用含水硫酸洗涤,随后用蒸馏水洗涤直到中性,从而制备每百万份硅烷醇(≡SiOH)含有最多100-300份几乎完全缩合的氢倍半硅氧烷树脂。过滤该溶液,除去不溶物质,然后蒸发至干,从而留下粉末形式的固体树脂状聚合物。
[0015]美国专利5010159(1991年4月23日)(同样在此通过参考将其引入)教导了水解氢化硅烷的另一方法,采用芳基磺酸水合物介质,将其溶解在烃溶剂内,形成树脂。可通过除去溶剂,回收粉末形式的固体树脂状聚合物。可通过在大气压下蒸馏掉溶剂,从而除去溶剂,形成含有40-80%树脂的浓缩物,和在真空与温和的加热下除去残留的溶剂。
[0016]在美国专利4999397(1991年3月12日)中公开了其他合适的树脂,其中包括根据日本Kokai专利JP 59-178749(1990年7月6日)、JP60-086017(1985年5月15日)和JP 63-107122(1988年5月12日)通过在酸性醇介质内水解烷氧基或酰氧基硅烷生产的那些树脂,所有这些在此通过参考引入。
[0017]可通过简单地在溶剂或溶剂混合物内溶解或分散先驱体含硅树脂,来形成树脂状聚合物的溶液。作为实例,可使用的一些合适的溶剂是:芳烃,例如苯、甲苯和二甲苯;烷烃,例如正庚烷、己烷、辛烷和十二烷;酮,例如甲乙酮和甲基异丁基酮(MIBK);直链聚二甲基硅氧烷,例如六甲基二硅氧烷、八甲基三硅氧烷、十甲基四硅氧烷及其混合物;环状聚二甲基硅氧烷,例如八甲基环四硅氧烷、十甲基环五硅氧烷、十二甲基环六硅氧烷及其混合物;酯,例如乙酸丁酯和乙酸异戊酯;或醚,例如二乙醚和己醚。一般地,使用足量的溶剂形成溶液,其范围典型地为树脂重量10-85%的固体含量。
[0018]本发明基于下述发现:诸如一氧化二氮(N2O)、氧化一氮(NO)、氧气(O2)、水蒸汽和类似物之类的氧化剂当在高温下固化成膜材料中使用时,常常引起在纳米级沟槽顶部内的成膜材料比在纳米级沟槽底部内的成膜材料变得更致密。在高温固化过程中,例如在沟槽顶部内的成膜材料接触氧化剂,之后氧化剂到达纳米级沟槽底部。结果是在沟槽顶部内的成膜材料发生氧化,之后在纳米级沟槽底部内的成膜材料被充分地氧化。这会妨碍充分致密和充分填充的纳米级沟槽的形成。在纳米级沟槽顶部内固化的成膜材料形成致密的表层,所述表层将阻止氧化剂和成膜材料任何进一步地渗透到纳米级沟槽内。结果,在纳米级沟槽底部内的成膜材料不可能充分地固化到与在纳米级沟槽顶部内的成膜材料相同的程度。
[0019]通过本发明的方法,将避免这一非所需的结果,该方法使得本领域的技术人员可在纳米级沟槽内获得充分固化的HSQ。该方法允许氧化剂和成膜材料充分地扩散和/或渗透到纳米级沟槽内,之后形成致密的表层。然后氧化剂能与HSQ成膜材料内的Si-H基反应,其结果是形成硅烷醇基。在相对低的温度范围内进行这些反应,所述低温范围允许氧化剂和成膜材料这二者移动到纳米级沟槽底部内。水蒸汽是用于低温固化的优选氧化剂。在低温下,具有较小的几率形成致密表层。水蒸汽因此可充分地渗透和/或扩散到纳米级沟槽底部内。水蒸汽氧化剂然后可如上所述与HSQ成膜材料内的SiH基反应,从而形成硅烷醇基。
[0020]水蒸汽温度应当维持在足够低的范围,以便不形成致密的表层,但仍然维持在足以允许水蒸汽和成膜材料渗透到纳米级沟槽深处的范围下。允许在低温下经充足的时间发生反应之后,两个低温固化步骤后是在氧化环境内第三高温退火步骤。因此,第三步引起成膜材料内硅烷醇基缩合,并在纳米级沟槽内形成氧化硅。因此获得显示出良好的耐湿法蚀刻的充分致密的纳米级沟槽。这表明可使用该方法在沟槽内生产致密的填充材料。
[0021]这三步固化的温度范围是(i)从20-25℃的室温和/或环境温度到100℃以供第一低温固化;(ii)100-400℃以供第二和/或热渗透低温固化;和(iii)800-900℃以供第三高温和/或退火固化。在作为优选氧化剂的水蒸汽存在下,进行第一低温固化和第二和/或热渗透低温固化。在作为优选氧化剂的水蒸汽或一氧化二氮存在下进行第三高温和/或退火固化。可使用其他常见的氧化剂,条件是其使用对所得晶片表面没有有害影响。可在400-800℃的温度下,在一氧化二氮存在下进一步致密化在半导体基底内的填充的氧化物沟槽。时间段允许在这三步的每一步中固化且致密化应当为30-60分钟。
[0022]基底是在其上具有沟槽的半导体基底。不具体地限定该半导体基底,和可以是在制造集成电路中所使用的任何半导体基底。例如,基底可以是硅片。通过旋涂沉积(SOD),施加成膜材料。当使用旋涂沉积时,条件取决于各种因素,其中包括通过该方法形成的膜的所需厚度和所选的特定成膜材料。典型地,在至少约500转/分钟(rpm)至约6000rpm的速度下旋转成膜材料沉积于其上的半导体基底。沉积时间为至少约5秒至约3分钟。以约0.4ml/cm2的量沉积成膜材料。然而,可调节旋转速度、旋转时间和所使用的成膜材料用量,以产生具有所需厚度的膜。例如,可调节所需厚度到约800纳米。
[0023]该方法可包括在SOD之后和在固化之前,除去所有或一部分溶剂的任选步骤。可通过任何方便的方式,例如在环境压力或者减压下加热,除去溶剂。可通过加热到至少约250℃至约400℃的温度下,除去溶剂。
[0024]该方法可生产厚度为至少约800nm的基本上没有裂纹的膜。该方法可生产具有良好机械强度的膜。该方法可生产介电常数最多约4的膜。该方法可生产含硅和氧的膜,其含量使得硅与氧的摩尔比为约1至约2。该方法生产在制造电子器件的工艺过程中具有良好的抗侵入的湿法蚀刻技术的膜。例如,可制备下述膜:当在室温下暴露于200∶1的氢氟酸水溶液内1分钟时,该膜的抗蚀刻性用在沟槽内膜的损失表达为70-100埃/分钟。
[0025]可使用以上所述的方法,在宽泛的应用中形成用作电介质层的膜。例如,可使用该方法,在电子器件内形成金属沉积前的(premetal)电介质(PMD)层,浅槽隔离(STI)、内层电介质(ILD)层和平面化层。
[0026]在形成动态随机存取存储器(DRAM)器件内的STI层中阐述此处所述的方法。在制造DRAM器件的典型方法中,硅片具有在其上的多个陶瓷栅极。这些栅极具有在其间的沟槽。长径比(W∶D)可以是1∶10,优选1∶8。这些沟槽的宽度可以在10-100纳米间变化。
[0027]除了DRAM器件以外,还可在其他器件中使用此处的方法。例如,可使用该方法,在LOGIC器件或者存储器件例如DRAM,或者静态随机存取存储器(SRAM)中形成电介质层。可使用该方法,在中央处理单元(CPU)器件内形成电介质层。CPU可具有10-12层电介质层。还可在LOGIC和存储器中使用该方法用于沟槽隔离,例如浅槽隔离(STI)。可使用该方法填充在半导体基底上的沟槽或者空穴,以隔离p-和n-接点,并防止掺杂剂迁移。
实施例
[0028]列出下述实施例以更详细地阐述本发明。
实施例1
[0029]使用在八甲基三硅氧烷中分别含有4wt%和8wt%HSQ的两种精细过滤的HSQ溶液。在硅片表面上旋涂该膜。在第一低温固化步骤中,在水蒸汽环境内,最初保持膜在100℃下30分钟。在第二低温固化步骤中,在水蒸汽环境内,经1小时使温度升高到250℃。在这两个低温固化步骤期间,水蒸汽保持在沟槽内并与HSQ反应。然后在第三高温固化步骤中,在水蒸汽或者一氧化二氮环境中,在800℃下进一步固化膜1小时。通过将膜暴露于200∶1的氢氟酸水溶液中60秒,进行蚀刻,并测定膜损失。在图1中示出了所得膜。
实施例2-对比
[0030]使用正常的氧化固化,但没有水蒸汽在800℃下重复实施例1。没有观察到膜的抗蚀刻性。在沟槽内的填充材料被完全除去。
实施例3
[0031]重复实施例1,和在一氧化二氮(N2O)环境下,进一步致密化在硅片的纳米级沟槽内的固化的HSQ膜。特别地,采用不同的温度测定在一氧化二氮环境内在硅片上涂布的HSQ树脂薄膜的固化。使用与实施例1所述相同的HF蚀刻工序,测定在纳米级沟槽内的抗湿法蚀刻性。每一次测定的工艺时间为1小时。如表1所示,与在氧气或者氮气环境下固化的HSQ膜相比,在HF稀溶液内,在一氧化二氮中固化的HSQ膜的膜损失减少。特别地,在800℃下,在一氧化二氮下固化的HSQ膜具有与热氧化物膜相当的膜损失。表1中热氧化物膜的数值是文献中的公开数据。表1还示出了在一氧化二氮下固化的HSQ膜的机械性能(即,硬度和模量)增加,这通过高的硬度和模量值来佐证。
表1-在不同的固化温度下固化的HSQ膜的薄膜性能
温度,氧化剂 | 200∶1HF湿法蚀刻1分钟,膜的损失(埃) | 模量(Gpa) | 硬度(Gpa) | 在1MHz下的介电常数 |
400℃,N2 | 2800 | 4.25 | 0.73 | 2.9 |
400℃,N2O | 324.8 | 12.3 | 1.72 | 3.2 |
550℃,N2O | 130.2 | 58.5 | 4.26 | 5.9 |
650℃,N2O | 92.4 | 65.0 | 4.91 | 5.5 |
750℃,N2O | 39.2 | 66.0 | 5.80 | 4.5 |
800℃,N2O | 22.4 | 73.0 | 6.70 | 4.2 |
800℃,O2 | 81.2 | 56.0 | 4.00 | 4.7 |
热氧化物 | 14 | 70.0 | 7.04 | 4.2 |
Claims (16)
1.一种填充在半导体基底内的沟槽的方法,该方法包括:
(i)在半导体基底上和在沟槽内分配成膜材料;
(ii)在第一低温下,在氧化剂存在下固化分配的成膜材料第一预定的时间段;
(iii)在第二低温下,在氧化剂存在下固化分配的成膜材料第二预定的时间段;
(iv)在第三高温下,在氧化剂存在下固化分配的成膜材料第三预定的时间段;和
(v)在半导体基底内形成填充的氧化物沟槽。
2.权利要求1的方法,其中成膜材料包括氢倍半硅氧烷的溶液。
3.权利要求1的方法,其中氧化剂选自一氧化二氮、氧化一氮、氧气和水蒸汽。
4.权利要求1的方法,其中通过旋涂沉积将成膜材料分配在半导体基底上和沟槽内。
5.权利要求1的方法,其中第一低温是从20-25℃至100℃。
6.权利要求1的方法,其中第二低温是100-400℃。
7.权利要求1的方法,其中第三高温是800-900℃。
8.权利要求1的方法,其中第一、第二和第三预定的时间段各自为30-60分钟。
9.权利要求1的方法,进一步包括(vi)在一氧化二氮存在下,在400-800℃的温度下,致密化在半导体基底内的填充的氧化物沟槽。
10.一种半导体基底,它具有通过权利要求1的方法制备的填充的沟槽。
11.一种填充在半导体基底内的沟槽的方法,该方法包括:
(i)在半导体基底上和在沟槽内分配氢倍半硅氧烷膜;
(ii)在从20-25℃至100℃的温度下,在氧化剂存在下固化分配的氢倍半硅氧烷第一预定的时间段;
(iii)在100-400℃的温度下,在氧化剂存在下固化分配的氢倍半硅氧烷第二预定的时间段;
(iv)在800-900℃的温度下,在氧化剂存在下固化分配的氢倍半硅氧烷第三预定的时间段;和
(v)在半导体基底内形成填充的氧化物沟槽。
12.权利要求11的方法,其中氧化剂选自一氧化二氮、氧化一氮、氧气和水蒸汽。
13.权利要求11的方法,其中通过旋涂沉积将氢倍半硅氧烷膜分配在半导体基底上和沟槽内。
14.权利要求11的方法,其中第一、第二和第三预定的时间段各自为30-60分钟。
15.权利要求11的方法,进一步包括(vi)在一氧化二氮存在下,在400-800℃的温度下,致密化在半导体基底内的填充的氧化物沟槽。
16.一种半导体基底,它具有通过权利要求11的方法制备的填充的沟槽。
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JPWO2009096603A1 (ja) * | 2008-02-01 | 2011-05-26 | Jsr株式会社 | トレンチアイソレーションの形成方法 |
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-
2006
- 2006-06-12 JP JP2008516898A patent/JP2008547194A/ja not_active Withdrawn
- 2006-06-12 US US11/919,109 patent/US20090032901A1/en not_active Abandoned
- 2006-06-12 EP EP06760541A patent/EP1891669A2/en not_active Withdrawn
- 2006-06-12 WO PCT/US2006/020851 patent/WO2006138055A2/en active Application Filing
- 2006-06-12 CN CNA2006800185478A patent/CN101185160A/zh active Pending
- 2006-06-12 KR KR1020077029377A patent/KR20080017368A/ko not_active Application Discontinuation
- 2006-06-15 TW TW095121470A patent/TW200707583A/zh unknown
Cited By (3)
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CN107393864A (zh) * | 2017-08-29 | 2017-11-24 | 睿力集成电路有限公司 | 一种隔离结构及其制造方法 |
CN108899300A (zh) * | 2017-08-29 | 2018-11-27 | 长鑫存储技术有限公司 | 一种隔离结构及其制造方法 |
CN108899300B (zh) * | 2017-08-29 | 2020-09-25 | 长鑫存储技术有限公司 | 一种隔离结构及其制造方法 |
Also Published As
Publication number | Publication date |
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KR20080017368A (ko) | 2008-02-26 |
EP1891669A2 (en) | 2008-02-27 |
WO2006138055A2 (en) | 2006-12-28 |
JP2008547194A (ja) | 2008-12-25 |
TW200707583A (en) | 2007-02-16 |
WO2006138055A3 (en) | 2007-08-02 |
US20090032901A1 (en) | 2009-02-05 |
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