DE3889849D1 - Verfahren zum bevorzugten Ätzen von polykristallinem Silicium. - Google Patents

Verfahren zum bevorzugten Ätzen von polykristallinem Silicium.

Info

Publication number
DE3889849D1
DE3889849D1 DE3889849T DE3889849T DE3889849D1 DE 3889849 D1 DE3889849 D1 DE 3889849D1 DE 3889849 T DE3889849 T DE 3889849T DE 3889849 T DE3889849 T DE 3889849T DE 3889849 D1 DE3889849 D1 DE 3889849D1
Authority
DE
Germany
Prior art keywords
polycrystalline silicon
preferentially etching
etching polycrystalline
preferentially
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3889849T
Other languages
English (en)
Other versions
DE3889849T2 (de
Inventor
Jasper William Dockrey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of DE3889849D1 publication Critical patent/DE3889849D1/de
Application granted granted Critical
Publication of DE3889849T2 publication Critical patent/DE3889849T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
DE3889849T 1987-11-02 1988-10-20 Verfahren zum bevorzugten Ätzen von polykristallinem Silicium. Expired - Fee Related DE3889849T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/115,307 US4799991A (en) 1987-11-02 1987-11-02 Process for preferentially etching polycrystalline silicon

Publications (2)

Publication Number Publication Date
DE3889849D1 true DE3889849D1 (de) 1994-07-07
DE3889849T2 DE3889849T2 (de) 1995-01-05

Family

ID=22360519

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3889849T Expired - Fee Related DE3889849T2 (de) 1987-11-02 1988-10-20 Verfahren zum bevorzugten Ätzen von polykristallinem Silicium.

Country Status (5)

Country Link
US (1) US4799991A (de)
EP (1) EP0314990B1 (de)
JP (1) JP2655336B2 (de)
KR (1) KR970011134B1 (de)
DE (1) DE3889849T2 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0286855A1 (de) * 1987-04-15 1988-10-19 BBC Brown Boveri AG Verfahren zum Aetzen von Vertiefungen in ein Siliziumsubstrat
US5316616A (en) * 1988-02-09 1994-05-31 Fujitsu Limited Dry etching with hydrogen bromide or bromine
JPH02177432A (ja) * 1988-12-28 1990-07-10 Fujitsu Ltd ドライ・エッチング方法
JP2673380B2 (ja) * 1990-02-20 1997-11-05 三菱電機株式会社 プラズマエッチングの方法
JP3127454B2 (ja) * 1990-08-08 2001-01-22 ソニー株式会社 シリコン系被エッチング材のエッチング方法
JPH0779102B2 (ja) * 1990-08-23 1995-08-23 富士通株式会社 半導体装置の製造方法
JP2964605B2 (ja) * 1990-10-04 1999-10-18 ソニー株式会社 ドライエッチング方法
US5228950A (en) * 1990-12-04 1993-07-20 Applied Materials, Inc. Dry process for removal of undesirable oxide and/or silicon residues from semiconductor wafer after processing
US5242536A (en) * 1990-12-20 1993-09-07 Lsi Logic Corporation Anisotropic polysilicon etching process
US5167762A (en) * 1991-01-02 1992-12-01 Micron Technology, Inc. Anisotropic etch method
US5338398A (en) * 1991-03-28 1994-08-16 Applied Materials, Inc. Tungsten silicide etch process selective to photoresist and oxide
KR100188455B1 (ko) * 1991-05-20 1999-06-01 이노우에 아키라 드라이 에칭방법
JP3179872B2 (ja) * 1991-12-19 2001-06-25 東京エレクトロン株式会社 エッチング方法
JP2574094B2 (ja) * 1992-02-27 1997-01-22 株式会社日本製鋼所 エッチング方法
US5378648A (en) * 1992-07-15 1995-01-03 Micron Technology, Inc. Situ stringer removal during polysilicon capacitor cell plate delineation
JP3009975B2 (ja) * 1992-11-30 2000-02-14 シャープ株式会社 シリコン薄膜のドライエッチング方法
US5342801A (en) * 1993-03-08 1994-08-30 National Semiconductor Corporation Controllable isotropic plasma etching technique for the suppression of stringers in memory cells
US5474947A (en) * 1993-12-27 1995-12-12 Motorola Inc. Nonvolatile memory process
JP2871460B2 (ja) * 1994-05-20 1999-03-17 株式会社日立製作所 シリコンのエッチング方法
US5593538A (en) * 1995-09-29 1997-01-14 Motorola, Inc. Method for etching a dielectric layer on a semiconductor
US5767018A (en) * 1995-11-08 1998-06-16 Advanced Micro Devices, Inc. Method of etching a polysilicon pattern
US5895273A (en) * 1997-06-27 1999-04-20 International Business Machines Corporation Silicon sidewall etching
US6136211A (en) * 1997-11-12 2000-10-24 Applied Materials, Inc. Self-cleaning etch process
US6322714B1 (en) * 1997-11-12 2001-11-27 Applied Materials Inc. Process for etching silicon-containing material on substrates
US6797188B1 (en) 1997-11-12 2004-09-28 Meihua Shen Self-cleaning process for etching silicon-containing material
US6872322B1 (en) 1997-11-12 2005-03-29 Applied Materials, Inc. Multiple stage process for cleaning process chambers
KR100282709B1 (ko) * 1998-08-28 2001-03-02 윤종용 반구형 실리콘을 이용한 캐패시터의 제조 방법
US7361287B2 (en) * 1999-04-30 2008-04-22 Robert Bosch Gmbh Method for etching structures in an etching body by means of a plasma
US6475915B1 (en) * 1999-10-19 2002-11-05 Advanced Micro Devices, Inc. Ono etch using CL2/HE chemistry
US6527968B1 (en) 2000-03-27 2003-03-04 Applied Materials Inc. Two-stage self-cleaning silicon etch process
US6905800B1 (en) 2000-11-21 2005-06-14 Stephen Yuen Etching a substrate in a process zone
US6852242B2 (en) 2001-02-23 2005-02-08 Zhi-Wen Sun Cleaning of multicompositional etchant residues
JP5037766B2 (ja) * 2001-09-10 2012-10-03 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
DE10309711A1 (de) * 2001-09-14 2004-09-16 Robert Bosch Gmbh Verfahren zum Einätzen von Strukturen in einem Ätzkörper mit einem Plasma
KR100423064B1 (ko) * 2002-03-21 2004-03-12 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US7078247B2 (en) * 2003-06-06 2006-07-18 International Business Machines Corporation Early detection of contact liner integrity by chemical reaction
KR100793607B1 (ko) * 2006-06-27 2008-01-10 매그나칩 반도체 유한회사 에피텍셜 실리콘 웨이퍼 및 그 제조방법
US8118946B2 (en) * 2007-11-30 2012-02-21 Wesley George Lau Cleaning process residues from substrate processing chamber components

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56144542A (en) * 1980-03-17 1981-11-10 Ibm Method of selectively reactively ion etching polycrystalline silicon for monocrsytalline silicon
US4471522A (en) * 1980-07-08 1984-09-18 International Business Machines Corporation Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes
DE3103177A1 (de) * 1981-01-30 1982-08-26 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von polysiliziumstrukturen bis in den 1 (my)m-bereich auf integrierte halbleiterschaltungen enthaltenden substraten durch plasmaaetzen
US4422897A (en) * 1982-05-25 1983-12-27 Massachusetts Institute Of Technology Process for selectively etching silicon
JPS58218121A (ja) * 1982-06-11 1983-12-19 Anelva Corp シリコンのドライエツチングモニタリング方法
US4417947A (en) * 1982-07-16 1983-11-29 Signetics Corporation Edge profile control during patterning of silicon by dry etching with CCl4 -O2 mixtures
US4426246A (en) * 1982-07-26 1984-01-17 Bell Telephone Laboratories, Incorporated Plasma pretreatment with BCl3 to remove passivation formed by fluorine-etch
JPS59189625A (ja) * 1983-04-13 1984-10-27 Nec Corp 半導体装置の製造方法
US4468285A (en) * 1983-12-22 1984-08-28 Advanced Micro Devices, Inc. Plasma etch process for single-crystal silicon with improved selectivity to silicon dioxide
US4490209B2 (en) * 1983-12-27 2000-12-19 Texas Instruments Inc Plasma etching using hydrogen bromide addition
JPS60145624A (ja) * 1984-01-10 1985-08-01 Nec Corp パタ−ンの形成方法
US4528066A (en) * 1984-07-06 1985-07-09 Ibm Corporation Selective anisotropic reactive ion etching process for polysilicide composite structures

Also Published As

Publication number Publication date
JPH01230237A (ja) 1989-09-13
EP0314990A2 (de) 1989-05-10
KR970011134B1 (ko) 1997-07-07
US4799991A (en) 1989-01-24
KR890008959A (ko) 1989-07-13
DE3889849T2 (de) 1995-01-05
JP2655336B2 (ja) 1997-09-17
EP0314990B1 (de) 1994-06-01
EP0314990A3 (en) 1989-09-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee