DE3889709D1 - Verfahren zum Ätzen von Gräben. - Google Patents

Verfahren zum Ätzen von Gräben.

Info

Publication number
DE3889709D1
DE3889709D1 DE3889709T DE3889709T DE3889709D1 DE 3889709 D1 DE3889709 D1 DE 3889709D1 DE 3889709 T DE3889709 T DE 3889709T DE 3889709 T DE3889709 T DE 3889709T DE 3889709 D1 DE3889709 D1 DE 3889709D1
Authority
DE
Germany
Prior art keywords
etching method
trench etching
trench
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3889709T
Other languages
English (en)
Other versions
DE3889709T2 (de
Inventor
Takushi Motoyama
Naomichi Abe
Satoru Mihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE3889709D1 publication Critical patent/DE3889709D1/de
Application granted granted Critical
Publication of DE3889709T2 publication Critical patent/DE3889709T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
DE3889709T 1987-10-29 1988-10-31 Verfahren zum Ätzen von Gräben. Expired - Fee Related DE3889709T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62274779A JPH01117034A (ja) 1987-10-29 1987-10-29 トレンチエッチング方法

Publications (2)

Publication Number Publication Date
DE3889709D1 true DE3889709D1 (de) 1994-06-30
DE3889709T2 DE3889709T2 (de) 1994-09-08

Family

ID=17546444

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3889709T Expired - Fee Related DE3889709T2 (de) 1987-10-29 1988-10-31 Verfahren zum Ätzen von Gräben.

Country Status (5)

Country Link
US (1) US5030316A (de)
EP (1) EP0314522B1 (de)
JP (1) JPH01117034A (de)
KR (1) KR910009611B1 (de)
DE (1) DE3889709T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4029912A1 (de) * 1990-09-21 1992-03-26 Philips Patentverwaltung Verfahren zur bildung mindestens eines grabens in einer substratschicht
FR2669466B1 (fr) * 1990-11-16 1997-11-07 Michel Haond Procede de gravure de couches de circuit integre a profondeur fixee et circuit integre correspondant.
EP0511448A1 (de) * 1991-04-30 1992-11-04 International Business Machines Corporation Verfahren und Vorrichtung zur in-situ und in-Linie Überwachung eines Graben-Herstellungsverfahrens
US5281305A (en) * 1992-05-22 1994-01-25 Northrop Corporation Method for the production of optical waveguides employing trench and fill techniques
US5465859A (en) * 1994-04-28 1995-11-14 International Business Machines Corporation Dual phase and hybrid phase shifting mask fabrication using a surface etch monitoring technique
US5998301A (en) * 1997-12-18 1999-12-07 Advanced Micro Devices, Inc. Method and system for providing tapered shallow trench isolation structure profile
TW398053B (en) * 1998-07-31 2000-07-11 United Microelectronics Corp Manufacturing of shallow trench isolation
DE10004394A1 (de) * 2000-02-02 2001-08-16 Infineon Technologies Ag Verfahren zur Grabenätzung in Halbleitermaterial
US20200135898A1 (en) * 2018-10-30 2020-04-30 International Business Machines Corporation Hard mask replenishment for etching processes
CN110316971B (zh) * 2019-07-03 2021-09-24 Tcl华星光电技术有限公司 蚀刻混切玻璃基板的方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4496425A (en) * 1984-01-30 1985-01-29 At&T Technologies, Inc. Technique for determining the end point of an etching process
JPS60251626A (ja) * 1984-05-28 1985-12-12 Mitsubishi Electric Corp エツチングの終点検出方法
JPS61115326A (ja) * 1984-11-12 1986-06-02 Oki Electric Ind Co Ltd 半導体基板のエツチング方法
JPS61232620A (ja) * 1985-04-09 1986-10-16 Matsushita Electronics Corp 半導体基板エツチング方法
JPS61232619A (ja) * 1985-04-09 1986-10-16 Matsushita Electronics Corp 半導体基板エツチング方法

Also Published As

Publication number Publication date
EP0314522A3 (en) 1990-04-18
EP0314522B1 (de) 1994-05-25
JPH01117034A (ja) 1989-05-09
KR890007400A (ko) 1989-06-19
DE3889709T2 (de) 1994-09-08
EP0314522A2 (de) 1989-05-03
US5030316A (en) 1991-07-09
KR910009611B1 (ko) 1991-11-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee