DE69635326D1 - Verfahren zum Ätzen von Silizium - Google Patents

Verfahren zum Ätzen von Silizium

Info

Publication number
DE69635326D1
DE69635326D1 DE69635326T DE69635326T DE69635326D1 DE 69635326 D1 DE69635326 D1 DE 69635326D1 DE 69635326 T DE69635326 T DE 69635326T DE 69635326 T DE69635326 T DE 69635326T DE 69635326 D1 DE69635326 D1 DE 69635326D1
Authority
DE
Germany
Prior art keywords
etching silicon
etching
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69635326T
Other languages
English (en)
Other versions
DE69635326T2 (de
Inventor
Young Hoon Lee
Keith Raymond Milkove
Stiebritz, Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE69635326D1 publication Critical patent/DE69635326D1/de
Application granted granted Critical
Publication of DE69635326T2 publication Critical patent/DE69635326T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
DE69635326T 1995-04-28 1996-04-09 Verfahren zum Ätzen von Silizium Expired - Lifetime DE69635326T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US431347 1995-04-28
US08/431,347 US5665203A (en) 1995-04-28 1995-04-28 Silicon etching method

Publications (2)

Publication Number Publication Date
DE69635326D1 true DE69635326D1 (de) 2005-12-01
DE69635326T2 DE69635326T2 (de) 2006-07-06

Family

ID=23711526

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69635326T Expired - Lifetime DE69635326T2 (de) 1995-04-28 1996-04-09 Verfahren zum Ätzen von Silizium

Country Status (6)

Country Link
US (1) US5665203A (de)
EP (1) EP0746015B1 (de)
JP (1) JPH08306672A (de)
KR (1) KR100193978B1 (de)
DE (1) DE69635326T2 (de)
TW (1) TW279250B (de)

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US6423475B1 (en) 1999-03-11 2002-07-23 Advanced Micro Devices, Inc. Sidewall formation for sidewall patterning of sub 100 nm structures
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US6200491B1 (en) 1999-03-23 2001-03-13 Xerox Corporation Fabrication process for acoustic lens array for use in ink printing
US6239006B1 (en) * 1999-07-09 2001-05-29 Advanced Micro Devices, Inc. Native oxide removal with fluorinated chemistry before cobalt silicide formation
US6451642B1 (en) * 1999-07-14 2002-09-17 Texas Instruments Incorporated Method to implant NMOS polycrystalline silicon in embedded FLASH memory applications
JP2001156045A (ja) 1999-11-26 2001-06-08 Kawasaki Steel Corp 半導体装置の製造方法および製造装置
US6613679B2 (en) * 1999-12-22 2003-09-02 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor device
US6949203B2 (en) * 1999-12-28 2005-09-27 Applied Materials, Inc. System level in-situ integrated dielectric etch process particularly useful for copper dual damascene
US6500357B1 (en) * 1999-12-28 2002-12-31 Applied Materials Inc. System level in-situ integrated dielectric etch process particularly useful for copper dual damascene
US6605543B1 (en) * 1999-12-30 2003-08-12 Koninklijke Philips Electronics N.V. Process to control etch profiles in dual-implanted silicon films
JP2001237218A (ja) 2000-02-21 2001-08-31 Nec Corp 半導体装置の製造方法
US6391788B1 (en) * 2000-02-25 2002-05-21 Applied Materials, Inc. Two etchant etch method
US6527968B1 (en) 2000-03-27 2003-03-04 Applied Materials Inc. Two-stage self-cleaning silicon etch process
US6514378B1 (en) 2000-03-31 2003-02-04 Lam Research Corporation Method for improving uniformity and reducing etch rate variation of etching polysilicon
EP1156519A1 (de) * 2000-05-16 2001-11-21 Semiconductor 300 GmbH & Co. KG Gateätzverfahren für 12 Zoll-Wafern
US6905800B1 (en) 2000-11-21 2005-06-14 Stephen Yuen Etching a substrate in a process zone
US6852242B2 (en) 2001-02-23 2005-02-08 Zhi-Wen Sun Cleaning of multicompositional etchant residues
KR100764248B1 (ko) * 2001-06-15 2007-10-05 동경 엘렉트론 주식회사 드라이 에칭 방법
US20040009667A1 (en) * 2002-02-07 2004-01-15 Etsuo Iijima Etching method
KR100871372B1 (ko) * 2002-09-27 2008-12-02 주식회사 하이닉스반도체 플래쉬 메모리 소자의 게이트 형성방법
JP3543968B1 (ja) * 2003-01-31 2004-07-21 沖電気工業株式会社 半導体装置の製造方法
US6909151B2 (en) * 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7446050B2 (en) * 2003-08-04 2008-11-04 Taiwan Semiconductor Manufacturing Co., Ltd. Etching and plasma treatment process to improve a gate profile
JP2005101403A (ja) * 2003-09-26 2005-04-14 Oki Electric Ind Co Ltd 半導体装置のドライエッチング方法
KR100540334B1 (ko) * 2003-12-31 2006-01-11 동부아남반도체 주식회사 반도체 소자의 게이트 형성 방법
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7192875B1 (en) 2004-10-29 2007-03-20 Lam Research Corporation Processes for treating morphologically-modified silicon electrode surfaces using gas-phase interhalogens
US7226869B2 (en) * 2004-10-29 2007-06-05 Lam Research Corporation Methods for protecting silicon or silicon carbide electrode surfaces from morphological modification during plasma etch processing
US7291286B2 (en) * 2004-12-23 2007-11-06 Lam Research Corporation Methods for removing black silicon and black silicon carbide from surfaces of silicon and silicon carbide electrodes for plasma processing apparatuses
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7858481B2 (en) 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7396711B2 (en) * 2005-12-27 2008-07-08 Intel Corporation Method of fabricating a multi-cornered film
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US20080182395A1 (en) * 2007-01-03 2008-07-31 Hynix Semiconductor Inc. Method for forming pattern in semiconductor device
JP2009099742A (ja) * 2007-10-16 2009-05-07 Toshiba Corp 半導体装置の製造方法
US8118946B2 (en) 2007-11-30 2012-02-21 Wesley George Lau Cleaning process residues from substrate processing chamber components
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KR0176715B1 (ko) * 1990-07-30 1999-04-15 오가 노리오 드라이에칭방법
US5242536A (en) * 1990-12-20 1993-09-07 Lsi Logic Corporation Anisotropic polysilicon etching process
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JP2910382B2 (ja) * 1992-03-09 1999-06-23 日本電気株式会社 半導体装置の製造方法
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Also Published As

Publication number Publication date
US5665203A (en) 1997-09-09
JPH08306672A (ja) 1996-11-22
EP0746015A3 (de) 1999-01-20
TW279250B (en) 1996-06-21
KR100193978B1 (ko) 1999-06-15
EP0746015B1 (de) 2005-10-26
EP0746015A2 (de) 1996-12-04
DE69635326T2 (de) 2006-07-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: DUSCHER, R., DIPL.-PHYS. DR.RER.NAT., PAT.-ANW., 7