DE3841927A1 - Verfahren zur herstellung einer halbleitervorrichtung mit einem elektrischen kontakt - Google Patents

Verfahren zur herstellung einer halbleitervorrichtung mit einem elektrischen kontakt

Info

Publication number
DE3841927A1
DE3841927A1 DE3841927A DE3841927A DE3841927A1 DE 3841927 A1 DE3841927 A1 DE 3841927A1 DE 3841927 A DE3841927 A DE 3841927A DE 3841927 A DE3841927 A DE 3841927A DE 3841927 A1 DE3841927 A1 DE 3841927A1
Authority
DE
Germany
Prior art keywords
forming
semiconductor
layer
polycrystalline silicon
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE3841927A
Other languages
German (de)
English (en)
Other versions
DE3841927C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html
Inventor
Yoshinori Okumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3841927A1 publication Critical patent/DE3841927A1/de
Application granted granted Critical
Publication of DE3841927C2 publication Critical patent/DE3841927C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
DE3841927A 1987-12-14 1988-12-13 Verfahren zur herstellung einer halbleitervorrichtung mit einem elektrischen kontakt Granted DE3841927A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62317808A JPH0750696B2 (ja) 1987-12-14 1987-12-14 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3841927A1 true DE3841927A1 (de) 1989-06-22
DE3841927C2 DE3841927C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-11-21

Family

ID=18092271

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3841927A Granted DE3841927A1 (de) 1987-12-14 1988-12-13 Verfahren zur herstellung einer halbleitervorrichtung mit einem elektrischen kontakt

Country Status (4)

Country Link
US (1) US4906591A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPH0750696B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR920004175B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3841927A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4110906A1 (de) * 1990-04-04 1991-10-17 Gold Star Electronics Verfahren zum herstellen von zellen mit zumindest einem selbstausgerichteten kondensatorkontakt und zellstruktur mit zumindest einem selbstausgerichteten kondensatorkontakt
DE4331549A1 (de) * 1993-09-16 1995-04-13 Gold Star Electronics Verfahren zur Herstellung einer ULSI-Halbleitereinrichtung
DE10149199A1 (de) * 2001-10-05 2003-04-24 Infineon Technologies Ag Speicherzellenfeld und Verfahren zu seiner Herstellung

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2954263B2 (ja) * 1990-03-22 1999-09-27 沖電気工業株式会社 半導体装置の製造方法
JP2720592B2 (ja) * 1990-09-25 1998-03-04 日本電気株式会社 半導体装置の製造方法
KR0166824B1 (ko) * 1995-12-19 1999-02-01 문정환 반도체 소자의 제조방법
US6017829A (en) 1997-04-01 2000-01-25 Micron Technology, Inc. Implanted conductor and methods of making
US5998294A (en) * 1998-04-29 1999-12-07 The United States Of America As Represented By The Secretary Of The Navy Method for forming improved electrical contacts on non-planar structures
US6300017B1 (en) * 1998-08-20 2001-10-09 Micron Technology, Inc. Stencil masks and methods of manufacturing stencil masks
US6187481B1 (en) 1998-08-20 2001-02-13 Micron Technology, Inc. Semiconductive material stencil mask and methods of manufacturing stencil masks from semiconductive material, utilizing different dopants
KR100905872B1 (ko) * 2007-08-24 2009-07-03 주식회사 하이닉스반도체 반도체 소자의 금속배선 형성 방법
JP2017168698A (ja) * 2016-03-17 2017-09-21 東芝メモリ株式会社 半導体記憶装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2422120A1 (de) * 1973-06-29 1975-01-23 Ibm Verfahren zur herstellung einer halbleiteranordnung
US4693925A (en) * 1984-03-01 1987-09-15 Advanced Micro Devices, Inc. Integrated circuit structure having intermediate metal silicide layer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54128668A (en) * 1978-03-30 1979-10-05 Toshiba Corp Manufacture for electronic component device
US4502206A (en) * 1983-11-18 1985-03-05 Rca Corporation Method of forming semiconductor contacts by implanting ions of neutral species at the interfacial region
JPS6246575A (ja) * 1985-08-23 1987-02-28 Sharp Corp 薄膜半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2422120A1 (de) * 1973-06-29 1975-01-23 Ibm Verfahren zur herstellung einer halbleiteranordnung
US4693925A (en) * 1984-03-01 1987-09-15 Advanced Micro Devices, Inc. Integrated circuit structure having intermediate metal silicide layer

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
JP 55-165681 (A). In: Patent Abstracts of Japan, Bd. 5, Nr. 44, (E-50), 24.3.1981 *
Kakumu, M. et.al.: Paspac with low contact resistance and high reliability in CMOS LSIs. In: Symposium on VLSI Technology, Digest of Technical Papers, 18.-21. Mai 1987, S. 77-78 *
Lindhard, J. et.al: Range Concepts and Heavy Ion Ranges. In: Mat.-Fys.Med., Dan. Vid. Selsk. 33, Nr. 14, 1963 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4110906A1 (de) * 1990-04-04 1991-10-17 Gold Star Electronics Verfahren zum herstellen von zellen mit zumindest einem selbstausgerichteten kondensatorkontakt und zellstruktur mit zumindest einem selbstausgerichteten kondensatorkontakt
DE4110906C2 (de) * 1990-04-04 1998-07-02 Gold Star Electronics Verfahren zum Herstellen von DRAM-Zellen mit zumindest einem selbstausgerichteten Kondensatorkontakt und Zellstruktur mit zumindest einem selbstausgerichteten Kondensatorkontakt
DE4331549A1 (de) * 1993-09-16 1995-04-13 Gold Star Electronics Verfahren zur Herstellung einer ULSI-Halbleitereinrichtung
DE10149199A1 (de) * 2001-10-05 2003-04-24 Infineon Technologies Ag Speicherzellenfeld und Verfahren zu seiner Herstellung
US6873000B2 (en) 2001-10-05 2005-03-29 Infineon Technologies Ag Storage cell field and method of producing the same
DE10149199B4 (de) * 2001-10-05 2006-05-18 Infineon Technologies Ag Speicherzellenfeld und Verfahren zu seiner Herstellung

Also Published As

Publication number Publication date
JPH01157522A (ja) 1989-06-20
US4906591A (en) 1990-03-06
JPH0750696B2 (ja) 1995-05-31
DE3841927C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1991-11-21
KR890011033A (ko) 1989-08-12
KR920004175B1 (ko) 1992-05-30

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee