DE3778973D1 - Halbleiterspeichergeraet. - Google Patents

Halbleiterspeichergeraet.

Info

Publication number
DE3778973D1
DE3778973D1 DE8787108508T DE3778973T DE3778973D1 DE 3778973 D1 DE3778973 D1 DE 3778973D1 DE 8787108508 T DE8787108508 T DE 8787108508T DE 3778973 T DE3778973 T DE 3778973T DE 3778973 D1 DE3778973 D1 DE 3778973D1
Authority
DE
Germany
Prior art keywords
row
cell array
memory cell
test signal
row decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787108508T
Other languages
English (en)
Inventor
Shinji C O Patent Divisi Saito
Shigeru C O Patent Divi Atsumi
Sumio C O Patent Divisi Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3778973D1 publication Critical patent/DE3778973D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/781—Masking faults in memories by using spares or by reconfiguring using programmable devices combined in a redundant decoder
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
DE8787108508T 1986-06-12 1987-06-12 Halbleiterspeichergeraet. Expired - Lifetime DE3778973D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61136838A JPS62293598A (ja) 1986-06-12 1986-06-12 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3778973D1 true DE3778973D1 (de) 1992-06-17

Family

ID=15184684

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787108508T Expired - Lifetime DE3778973D1 (de) 1986-06-12 1987-06-12 Halbleiterspeichergeraet.

Country Status (4)

Country Link
US (1) US4860260A (de)
EP (1) EP0249903B1 (de)
JP (1) JPS62293598A (de)
DE (1) DE3778973D1 (de)

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DE3728521A1 (de) * 1987-08-26 1989-03-09 Siemens Ag Anordnung und verfahren zur feststellung und lokalisierung von fehlerhaften schaltkreisen eines speicherbausteins
DE68928112T2 (de) * 1988-03-18 1997-11-20 Toshiba Kawasaki Kk Masken-rom mit Ersatzspeicherzellen
GB2222461B (en) * 1988-08-30 1993-05-19 Mitsubishi Electric Corp On chip testing of semiconductor memory devices
JP2741878B2 (ja) * 1988-11-25 1998-04-22 富士通株式会社 メモリデバイス試験装置
US5289417A (en) * 1989-05-09 1994-02-22 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with redundancy circuit
JP2547633B2 (ja) * 1989-05-09 1996-10-23 三菱電機株式会社 半導体記憶装置
JP2773271B2 (ja) * 1989-07-26 1998-07-09 日本電気株式会社 半導体記憶装置
US4975601A (en) * 1989-09-29 1990-12-04 Sgs-Thomson Microelectronics, Inc. User-writable random access memory logic block for programmable logic devices
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JP2838425B2 (ja) * 1990-01-08 1998-12-16 三菱電機株式会社 半導体記憶装置
US5134616A (en) * 1990-02-13 1992-07-28 International Business Machines Corporation Dynamic ram with on-chip ecc and optimized bit and word redundancy
US5053999A (en) * 1990-03-28 1991-10-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having redundancy and capable of sequentially selecting memory cell lines
US5163168A (en) * 1990-03-30 1992-11-10 Matsushita Electric Industrial Co., Ltd. Pulse signal generator and redundancy selection signal generator
DE69129882T2 (de) * 1990-06-19 1999-03-04 Texas Instruments Inc Assoziatives DRAM-Redundanzschema mit variabler Satzgrösse
JP2899374B2 (ja) * 1990-07-16 1999-06-02 沖電気工業株式会社 半導体メモリのデコーダチェック回路
US5297086A (en) * 1990-07-31 1994-03-22 Texas Instruments Incorporated Method for initializing redundant circuitry
JP2619170B2 (ja) * 1990-10-02 1997-06-11 株式会社東芝 半導体メモリ及びその試験方法
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US5293564A (en) * 1991-04-30 1994-03-08 Texas Instruments Incorporated Address match scheme for DRAM redundancy scheme
JPH05109292A (ja) * 1991-10-14 1993-04-30 Toshiba Corp 不揮発性半導体記憶装置
JP3040625B2 (ja) * 1992-02-07 2000-05-15 松下電器産業株式会社 半導体記憶装置
JP2923114B2 (ja) * 1992-02-18 1999-07-26 株式会社沖マイクロデザイン宮崎 冗長デコーダ回路
JP2978329B2 (ja) * 1992-04-21 1999-11-15 三菱電機株式会社 半導体メモリ装置及びそのビット線の短絡救済方法
JPH0684394A (ja) * 1992-09-04 1994-03-25 Nec Corp 半導体メモリ回路
FR2699301B1 (fr) * 1992-12-16 1995-02-10 Sgs Thomson Microelectronics Procédé de traitement d'éléments défectueux dans une mémoire.
JPH06215590A (ja) * 1993-01-13 1994-08-05 Nec Ic Microcomput Syst Ltd フラッシュ消去型不揮発性メモリ
JP3293935B2 (ja) * 1993-03-12 2002-06-17 株式会社東芝 並列ビットテストモード内蔵半導体メモリ
US5377146A (en) * 1993-07-23 1994-12-27 Alliance Semiconductor Corporation Hierarchical redundancy scheme for high density monolithic memories
US5404331A (en) * 1993-07-30 1995-04-04 Sgs-Thomson Microelectronics, Inc. Redundancy element check in IC memory without programming substitution of redundant elements
US6101618A (en) * 1993-12-22 2000-08-08 Stmicroelectronics, Inc. Method and device for acquiring redundancy information from a packaged memory chip
KR0133832B1 (ko) * 1993-12-28 1998-04-23 김주용 리던던시 로오/컬럼 프리테스트 장치
DE69521493T2 (de) * 1995-04-04 2001-10-11 St Microelectronics Srl Selektiver Sicherungskodierer
JP3774500B2 (ja) * 1995-05-12 2006-05-17 株式会社ルネサステクノロジ 半導体記憶装置
US5592422A (en) * 1995-06-07 1997-01-07 Sgs-Thomson Microelectronics, Inc. Reduced pin count stress test circuit for integrated memory devices and method therefor
JPH0935493A (ja) * 1995-07-15 1997-02-07 Toshiba Corp 半導体メモリ装置、マイクロコントローラ及び半導体メモリ装置の製造方法
JP3865828B2 (ja) * 1995-11-28 2007-01-10 株式会社ルネサステクノロジ 半導体記憶装置
US5631868A (en) * 1995-11-28 1997-05-20 International Business Machines Corporation Method and apparatus for testing redundant word and bit lines in a memory array
US5841709A (en) * 1995-12-29 1998-11-24 Stmicroelectronics, Inc. Memory having and method for testing redundant memory cells
EP0801401B1 (de) * 1996-04-02 2003-08-27 STMicroelectronics, Inc. Prüfung und Reparatur einer eingebetteten Speicherschaltung
US5841784A (en) * 1996-04-02 1998-11-24 Stmicroelectronics, Inc. Testing and repair of embedded memory
JP3104621B2 (ja) * 1996-07-04 2000-10-30 日本電気株式会社 半導体集積回路装置
JP2002501654A (ja) 1997-05-30 2002-01-15 ミクロン テクノロジー，インコーポレイテッド ２５６Ｍｅｇダイナミックランダムアクセスメモリ
JPH117761A (ja) * 1997-06-13 1999-01-12 Toshiba Corp 画像用メモリ
KR19990018125A (ko) * 1997-08-26 1999-03-15 윤종용 Ic칩 검사용 테스터데이타 압축방법과 그 압축장치 및 ic칩용 테스터장치와 그 테스터방법
US6195762B1 (en) * 1998-06-24 2001-02-27 Micron Techonology, Inc. Circuit and method for masking a dormant memory cell
US6222760B1 (en) * 2000-07-25 2001-04-24 Micon Design Technology Co. Ltd OTP (one time programmable) micro-controller
JP3506377B2 (ja) * 2001-04-09 2004-03-15 松下電器産業株式会社 半導体装置およびその製造方法
JP2003203496A (ja) * 2002-01-08 2003-07-18 Mitsubishi Electric Corp 半導体記憶装置
US6920072B2 (en) * 2003-02-28 2005-07-19 Union Semiconductor Technology Corporation Apparatus and method for testing redundant memory elements
US20070279975A1 (en) * 2006-06-06 2007-12-06 Hudgens Stephen J Refreshing a phase change memory
JP5605978B2 (ja) * 2008-02-26 2014-10-15 ピーエスフォー ルクスコ エスエイアールエル 積層メモリ
KR20120003247A (ko) * 2010-07-02 2012-01-10 주식회사 하이닉스반도체 테스트 신호 생성장치, 이를 이용하는 반도체 메모리 장치 및 이의 멀티 비트 테스트 방법
US9385054B2 (en) * 2013-11-08 2016-07-05 Semiconductor Energy Laboratory Co., Ltd. Data processing device and manufacturing method thereof
KR20170055222A (ko) 2015-11-11 2017-05-19 삼성전자주식회사 리페어 단위 변경 기능을 가지는 메모리 장치 및 메모리 시스템
KR102567134B1 (ko) * 2018-10-01 2023-08-16 삼성전자주식회사 엑스선 조사량 측정 장치, 이를 포함하는 반도체 메모리 장치 및 반도체 메모리 장치의 테스트 방법

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JPS5564699A (en) * 1978-11-09 1980-05-15 Matsushita Electric Ind Co Ltd Semiconductor integrated-circuit memory
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US4358833A (en) * 1980-09-30 1982-11-09 Intel Corporation Memory redundancy apparatus for single chip memories
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JPS59107493A (ja) * 1982-12-09 1984-06-21 Ricoh Co Ltd テスト回路付きｅｐｒｏｍメモリ装置
JPS59168995A (ja) * 1983-03-17 1984-09-22 Mitsubishi Electric Corp 記憶装置
JPS59213099A (ja) * 1983-05-16 1984-12-01 Matsushita Electric Ind Co Ltd 集積回路装置
DE3318564A1 (de) * 1983-05-20 1984-11-22 Siemens AG, 1000 Berlin und 8000 München Integrierte digitale mos-halbleiterschaltung
JPH0666120B2 (ja) * 1983-11-09 1994-08-24 株式会社東芝 半導体記憶装置の冗長部
US4549101A (en) * 1983-12-01 1985-10-22 Motorola, Inc. Circuit for generating test equalization pulse
JPS60211700A (ja) * 1984-04-05 1985-10-24 Nec Corp 読出し専用メモリ
JPS60253088A (ja) * 1984-05-30 1985-12-13 Mitsubishi Electric Corp 半導体記憶装置
JPS61289600A (ja) * 1985-06-17 1986-12-19 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
JPS62293598A (ja) 1987-12-21
EP0249903B1 (de) 1992-05-13
US4860260A (en) 1989-08-22
EP0249903A3 (en) 1989-10-25
JPH0468719B2 (de) 1992-11-04
EP0249903A2 (de) 1987-12-23

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Legal Events

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8320 Willingness to grant licences declared (paragraph 23)