DE3683705D1 - Verfahren und anordnung zur auffrischung einer dynamischen halbleiterspeicheranordnung. - Google Patents

Verfahren und anordnung zur auffrischung einer dynamischen halbleiterspeicheranordnung.

Info

Publication number
DE3683705D1
DE3683705D1 DE8686111139T DE3683705T DE3683705D1 DE 3683705 D1 DE3683705 D1 DE 3683705D1 DE 8686111139 T DE8686111139 T DE 8686111139T DE 3683705 T DE3683705 T DE 3683705T DE 3683705 D1 DE3683705 D1 DE 3683705D1
Authority
DE
Germany
Prior art keywords
column address
arrangement
strobe signal
address strobe
refreshing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686111139T
Other languages
English (en)
Inventor
Masao Takuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3683705D1 publication Critical patent/DE3683705D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
DE8686111139T 1985-08-16 1986-08-12 Verfahren und anordnung zur auffrischung einer dynamischen halbleiterspeicheranordnung. Expired - Fee Related DE3683705D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60179274A JPH087995B2 (ja) 1985-08-16 1985-08-16 ダイナミツク半導体記憶装置のリフレツシユ方法および装置

Publications (1)

Publication Number Publication Date
DE3683705D1 true DE3683705D1 (de) 1992-03-12

Family

ID=16062974

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686111139T Expired - Fee Related DE3683705D1 (de) 1985-08-16 1986-08-12 Verfahren und anordnung zur auffrischung einer dynamischen halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4758992A (de)
EP (1) EP0212547B1 (de)
JP (1) JPH087995B2 (de)
KR (1) KR900002661B1 (de)
DE (1) DE3683705D1 (de)

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JPS6355797A (ja) * 1986-08-27 1988-03-10 Fujitsu Ltd メモリ
JPS6432489A (en) * 1987-07-27 1989-02-02 Matsushita Electronics Corp Memory device
JPH01124195A (ja) * 1987-11-09 1989-05-17 Sharp Corp セルフリフレッシュ方式
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
US4980888A (en) * 1988-09-12 1990-12-25 Digital Equipment Corporation Memory testing system
JPH02232736A (ja) * 1989-02-03 1990-09-14 Digital Equip Corp <Dec> システムモジュール間のｄｒａｍ制御信号のエラー検査を行なう方法及び手段
CA2011518C (en) * 1989-04-25 1993-04-20 Ronald N. Fortino Distributed cache dram chip and control method
JPH081747B2 (ja) * 1989-05-08 1996-01-10 三菱電機株式会社 半導体記憶装置およびその動作方法
US5907512A (en) * 1989-08-14 1999-05-25 Micron Technology, Inc. Mask write enablement for memory devices which permits selective masked enablement of plural segments
US5127014A (en) * 1990-02-13 1992-06-30 Hewlett-Packard Company Dram on-chip error correction/detection
DE69128061T2 (de) * 1990-08-30 1998-03-26 Nec Corp Halbleiterspeicheranordnung
JP3225533B2 (ja) * 1991-04-11 2001-11-05 日本電気株式会社 ダイナミック型半導体メモリ装置
KR950009390B1 (ko) * 1992-04-22 1995-08-21 삼성전자주식회사 반도체 메모리장치의 리프레시 어드레스 테스트회로
KR100214262B1 (ko) * 1995-10-25 1999-08-02 김영환 메모리 장치
US5758188A (en) * 1995-11-21 1998-05-26 Quantum Corporation Synchronous DMA burst transfer protocol having the peripheral device toggle the strobe signal such that data is latched using both edges of the strobe signal
KR100218733B1 (ko) * 1996-04-04 1999-09-01 김영환 싱크로노스 디램의 카스신호 발생기
JPH10177800A (ja) * 1996-10-21 1998-06-30 Texas Instr Inc <Ti> エラー訂正ダイナミック・メモリ及びそのエラー訂正方法
JP3177207B2 (ja) 1998-01-27 2001-06-18 インターナショナル・ビジネス・マシーンズ・コーポレ−ション リフレッシュ間隔制御装置及び方法、並びにコンピュータ
KR100253410B1 (ko) * 1998-02-20 2000-05-01 김영환 오토 리프레시 제어회로
JP4707803B2 (ja) * 2000-07-10 2011-06-22 エルピーダメモリ株式会社 エラーレート判定方法と半導体集積回路装置
JP2002056671A (ja) * 2000-08-14 2002-02-22 Hitachi Ltd ダイナミック型ｒａｍのデータ保持方法と半導体集積回路装置
AU1142001A (en) * 2000-10-19 2002-04-29 Dsm N.V. Protein hydrolysates
US20030115538A1 (en) * 2001-12-13 2003-06-19 Micron Technology, Inc. Error correction in ROM embedded DRAM
JP2006073062A (ja) * 2004-08-31 2006-03-16 Toshiba Corp 半導体記憶装置
JP2007133986A (ja) * 2005-11-11 2007-05-31 Nec Electronics Corp 半導体記憶装置
DE102006028943B4 (de) * 2006-06-23 2008-07-24 Infineon Technologies Ag Verfahren zum Betreiben eines flüchtigen Schreib-Lese-Speichers als Detektor und Schaltungsanordnung
KR101046304B1 (ko) * 2006-10-20 2011-07-05 후지쯔 가부시끼가이샤 메모리 장치 및 리프레시 조정 방법
CN101796497B (zh) 2007-07-18 2012-03-21 富士通株式会社 存储器刷新装置和存储器刷新方法
KR101653568B1 (ko) * 2009-07-03 2016-09-02 삼성전자주식회사 부분 셀프 리플레시 모드에서 전류 소모를 줄일 수 있는 반도체 메모리 장치
US8738993B2 (en) 2010-12-06 2014-05-27 Intel Corporation Memory device on the fly CRC mode
KR101873526B1 (ko) 2011-06-09 2018-07-02 삼성전자주식회사 에러 정정회로를 구비한 온 칩 데이터 스크러빙 장치 및 방법
JP5978860B2 (ja) * 2012-08-31 2016-08-24 富士通株式会社 情報処理装置、メモリ制御ユニット、メモリ制御方法および制御プログラム
KR102140592B1 (ko) * 2013-10-18 2020-08-03 에스케이하이닉스 주식회사 데이터 저장 장치
US10665305B2 (en) * 2015-09-09 2020-05-26 Toshiba Memory Corporation Host device connectable to memory device performing patrol read and memory device performing patrol read
KR102658230B1 (ko) 2018-06-01 2024-04-17 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 반도체 메모리 장치의 동작 방법
KR20210026201A (ko) 2019-08-29 2021-03-10 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 이의 리페어 제어 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4183096A (en) * 1978-05-25 1980-01-08 Bell Telephone Laboratories, Incorporated Self checking dynamic memory system
US4319356A (en) * 1979-12-19 1982-03-09 Ncr Corporation Self-correcting memory system
US4412314A (en) * 1980-06-02 1983-10-25 Mostek Corporation Semiconductor memory for use in conjunction with error detection and correction circuit
US4542454A (en) * 1983-03-30 1985-09-17 Advanced Micro Devices, Inc. Apparatus for controlling access to a memory

Also Published As

Publication number Publication date
KR870002580A (ko) 1987-03-31
EP0212547A3 (en) 1989-01-25
KR900002661B1 (ko) 1990-04-21
EP0212547B1 (de) 1992-01-29
JPS6254892A (ja) 1987-03-10
JPH087995B2 (ja) 1996-01-29
EP0212547A2 (de) 1987-03-04
US4758992A (en) 1988-07-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee