JPS55163685A - Memory control device - Google Patents

Memory control device

Info

Publication number
JPS55163685A
JPS55163685A JP6910079A JP6910079A JPS55163685A JP S55163685 A JPS55163685 A JP S55163685A JP 6910079 A JP6910079 A JP 6910079A JP 6910079 A JP6910079 A JP 6910079A JP S55163685 A JPS55163685 A JP S55163685A
Authority
JP
Japan
Prior art keywords
rewriting
register
address
refreshing
memory module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6910079A
Other languages
Japanese (ja)
Inventor
Mamoru Araki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6910079A priority Critical patent/JPS55163685A/en
Publication of JPS55163685A publication Critical patent/JPS55163685A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To ensure the automatic correction to the errors occurring intermittently as well as perform the rewriting according to the error frequency, by carrying out the rewriting to the volatile memory module every fixed interval and via the rewriting means and subsequently to the refreshing action. CONSTITUTION:The address advances in the refreshing period and via refresh control circuit 80, refresh address register 81 and address register 30 each. Memory module 50 is refreshed in sequence and every line, and the refreshing of all lines is repeated in the fixed cycle. Circuit 80 perform the refreshing action with every necessary cycle among all cycles and then carries out the rewriting to memory module 50 according to the address the advance of which is set to register 30 and via rewriting address register 91. In that case, the reading data of reading register 50 is detected and corrected at error detecting/correcting circuit 70, and the rewriting is carried out for the corrected data which is set to writing data register 41 via data selector 40. Thus the errors of the high-density memory which occur intermittently are corrected automatically in accordance with the error frequency.
JP6910079A 1979-06-01 1979-06-01 Memory control device Pending JPS55163685A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6910079A JPS55163685A (en) 1979-06-01 1979-06-01 Memory control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6910079A JPS55163685A (en) 1979-06-01 1979-06-01 Memory control device

Publications (1)

Publication Number Publication Date
JPS55163685A true JPS55163685A (en) 1980-12-19

Family

ID=13392857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6910079A Pending JPS55163685A (en) 1979-06-01 1979-06-01 Memory control device

Country Status (1)

Country Link
JP (1) JPS55163685A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008047443A1 (en) 2006-10-20 2008-04-24 Fujitsu Limited Memory device and refresh adjusting method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008047443A1 (en) 2006-10-20 2008-04-24 Fujitsu Limited Memory device and refresh adjusting method
US8539310B2 (en) 2006-10-20 2013-09-17 Fujitsu Limited Memory device and refresh adjusting method

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