JPS6426952A - Soft error correcting circuit - Google Patents

Soft error correcting circuit

Info

Publication number
JPS6426952A
JPS6426952A JP62184076A JP18407687A JPS6426952A JP S6426952 A JPS6426952 A JP S6426952A JP 62184076 A JP62184076 A JP 62184076A JP 18407687 A JP18407687 A JP 18407687A JP S6426952 A JPS6426952 A JP S6426952A
Authority
JP
Japan
Prior art keywords
error
group
data
correcting circuit
error correcting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62184076A
Other languages
Japanese (ja)
Inventor
Masazumi Minaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62184076A priority Critical patent/JPS6426952A/en
Publication of JPS6426952A publication Critical patent/JPS6426952A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To reduce the scale of a soft error correcting circuit by using one of two system memories to correct the multiple errors. CONSTITUTION:When the data 2 read out of a memory group 1 has an error, an error correcting circuit 3 corrects a single error and delivers the error correction output 4. Then an error detecting pulse 5 is supplied to the group 1. In this case, the data input of the group 1 is turned into the data output 8 of a memory group 7. Then an error non-detecting pulse 6 is supplied to the group 7 from the circuit 3 in case no error is detected at the circuit 3 where the correct data is written again. The memory group 7 uses the output 4 as the data input and writes data again by the pulse 6.
JP62184076A 1987-07-23 1987-07-23 Soft error correcting circuit Pending JPS6426952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62184076A JPS6426952A (en) 1987-07-23 1987-07-23 Soft error correcting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62184076A JPS6426952A (en) 1987-07-23 1987-07-23 Soft error correcting circuit

Publications (1)

Publication Number Publication Date
JPS6426952A true JPS6426952A (en) 1989-01-30

Family

ID=16146967

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62184076A Pending JPS6426952A (en) 1987-07-23 1987-07-23 Soft error correcting circuit

Country Status (1)

Country Link
JP (1) JPS6426952A (en)

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