JPS5668997A - Error correction system - Google Patents
Error correction systemInfo
- Publication number
- JPS5668997A JPS5668997A JP14259279A JP14259279A JPS5668997A JP S5668997 A JPS5668997 A JP S5668997A JP 14259279 A JP14259279 A JP 14259279A JP 14259279 A JP14259279 A JP 14259279A JP S5668997 A JPS5668997 A JP S5668997A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- bit error
- memory
- error correction
- writing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To realize a correction even for the 2-bit error due to the overlap of the soft and hard errors, by adding the data inverting circuit to the ECC circuit when the reading and writing are carried out for a memory.
CONSTITUTION: The 2-bit error correction circuit 1 is inserted in case the central processor CPU is connected to the memory array 5 via the memory control unit MiC. The circuit 1 consists of the ECC circuit 2 which detects the 2-bit error and corrects the 1-bit error, data inverting circuit 3 and timing control circuit 4 each. In case the 2-bit error is detected through the ECC circuit 2 when the memory is read out of the array 5, the reading data is inverted through the circuit 3 to perform the writing and rereading. Then the reading data is inverted again to correct the hard error, and furthermore an error correction is given through the circuit 2 when the 1-bit error remains.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14259279A JPS5668997A (en) | 1979-11-02 | 1979-11-02 | Error correction system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14259279A JPS5668997A (en) | 1979-11-02 | 1979-11-02 | Error correction system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5668997A true JPS5668997A (en) | 1981-06-09 |
Family
ID=15318884
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14259279A Pending JPS5668997A (en) | 1979-11-02 | 1979-11-02 | Error correction system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5668997A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010092459A (en) * | 2008-07-17 | 2010-04-22 | Marvell World Trade Ltd | Data recovery in solid state memory device |
-
1979
- 1979-11-02 JP JP14259279A patent/JPS5668997A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010092459A (en) * | 2008-07-17 | 2010-04-22 | Marvell World Trade Ltd | Data recovery in solid state memory device |
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