JPS567299A - Error correcting circuit - Google Patents

Error correcting circuit

Info

Publication number
JPS567299A
JPS567299A JP8001079A JP8001079A JPS567299A JP S567299 A JPS567299 A JP S567299A JP 8001079 A JP8001079 A JP 8001079A JP 8001079 A JP8001079 A JP 8001079A JP S567299 A JPS567299 A JP S567299A
Authority
JP
Japan
Prior art keywords
memory
error
output
bit
dec
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8001079A
Other languages
Japanese (ja)
Inventor
Shozo Taniguchi
Kiyokatsu Iijima
Takahiro Sakuraba
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8001079A priority Critical patent/JPS567299A/en
Publication of JPS567299A publication Critical patent/JPS567299A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To facilitate correction of multi-bit errors of a memory to improve reliability, by adding an error register, where information for discrimination of error bits is stored, and a one-bit alternative memory, in the memory unit.
CONSTITUTION: When a correctable error is detected in the read output of memory M, the error syndrome is calculated by circuit SG, and the error bit position is decoded by decoder DEC, and the output of read data selecting circuit RS is corrected by DC, and simultaneously, the error bit discrimination signal of the DEC is stored in error register EL. Control circuit CNT causes EL to output memory information by the output of SG and selects the write bit from external unit 2 to M afterward and writes it into alternative memory MA. For the M read operation, RS selects the output of MA by memory information of EL, and corrected data is output to unit 2 through circuits SG, DEC and DC.
COPYRIGHT: (C)1981,JPO&Japio
JP8001079A 1979-06-25 1979-06-25 Error correcting circuit Pending JPS567299A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8001079A JPS567299A (en) 1979-06-25 1979-06-25 Error correcting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8001079A JPS567299A (en) 1979-06-25 1979-06-25 Error correcting circuit

Publications (1)

Publication Number Publication Date
JPS567299A true JPS567299A (en) 1981-01-24

Family

ID=13706346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8001079A Pending JPS567299A (en) 1979-06-25 1979-06-25 Error correcting circuit

Country Status (1)

Country Link
JP (1) JPS567299A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582322A (en) * 1981-06-30 1983-01-07 Nitto Electric Ind Co Ltd Epoxy resin composition for encapsulation of semiconductor
JPS6061837A (en) * 1983-09-13 1985-04-09 Ibm Error corrector
JPS63160255A (en) * 1986-12-23 1988-07-04 Nitto Electric Ind Co Ltd Semiconductor device
JPH01251146A (en) * 1988-03-31 1989-10-06 Nec Corp Bit error correcting device
JPH03198135A (en) * 1989-12-22 1991-08-29 Internatl Business Mach Corp <Ibm> Fault margin memory system and its operation method

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582322A (en) * 1981-06-30 1983-01-07 Nitto Electric Ind Co Ltd Epoxy resin composition for encapsulation of semiconductor
JPS6217604B2 (en) * 1981-06-30 1987-04-18 Nitto Electric Ind Co
JPS6061837A (en) * 1983-09-13 1985-04-09 Ibm Error corrector
JPS63160255A (en) * 1986-12-23 1988-07-04 Nitto Electric Ind Co Ltd Semiconductor device
JPH01251146A (en) * 1988-03-31 1989-10-06 Nec Corp Bit error correcting device
JPH03198135A (en) * 1989-12-22 1991-08-29 Internatl Business Mach Corp <Ibm> Fault margin memory system and its operation method

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