JPH01251146A - Bit error correcting device - Google Patents

Abstract

PURPOSE:To substantially correct even plural bit errors by preparing spare bits in a memory and replacing an error bit with a spare bit when a 1-bit error occurs. CONSTITUTION:Data MD0-MD31 of 32 bits and check codes C0-C6 are read out of a memory 10 and inputted to a bit error correcting circuit (ECC circuit) 20. Then the circuit 20 produces a syndrome from the input data. If the data MD1 is erroneous, the corresponding bit is erroneous and equal to the neck syndrome of a 1-bit error. Then the circuit 20 gives an instruction to a correcting circuit 30 based on said error information to invert only the data MD1. Thus the read data D0-D31 are corrected. At the same time, the circuit 20 sends the error bit number information to a selector 40. The selector 40 starts a switch circuit 501 (corresponding to data MD1) among those switch circuits 500-531 based on the input information and switches the circuit 501 to a space MDSBY bit.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention is applied to storage control program type main storage devices, etc., and is particularly applicable to memory bit error correction circuits (hereinafter referred to as EC
The present invention relates to a bit error correction device using a C circuit (abbreviated as C circuit).

[Prior Art] The ECC circuit has a bit error correction function, and for this purpose, it generates a check code when writing data, writes the check code together with the data in the main memory, and when reading data, it generates a check code along with the data. A syndrome code is generated by the check code, and based on the result, the presence or absence of a bit error is determined and d1 is corrected.

FIG. 3 shows a conventional FCC correction method.

This figure shows the case of 1-bit error correction and 2-bit error detection with a data length of 32 bits and a check bit length of 7 bits.

In this case, data (MDO to MD31
) and check data (Co-C6), and EC
In the C circuit 2, a syndrome code and information on the presence or absence of a 1-pit error are generated in a circuit 21, and errors are corrected by performing exclusive logic with the read data in exclusive OR circuits 300 to 331 in a correction circuit 3. Ta.

[Problems to be solved] In the conventional method described above, 7 or 8 check bits are required for 32-bit data length for 1-bit error correction and 2-bit error detection. The disadvantage is that the number of bits increases further. This lick is 1
Bit error correction and 2-bit error detection methods are commonly used.

However, the conventional method has the disadvantage that if maintenance work (element replacement, etc.) is not performed immediately after a 1-bit error occurs, a 2-bit error will occur if a new pit error occurs, so the error can only be detected and cannot be corrected. Ta.

Therefore, the 1"J objective of the present invention is to solve the above-mentioned conventional problems and to
To provide a bit error correction device that can utilize a 1-bit error correction function even when a bit error occurs (in the case of a total of 2 bit errors), and thereby can substantially correct up to multiple bit errors.

[Means for solving problems] The present invention provides E CC [i! A bit error correction device using a circuit includes a memory having a configuration □ in which spare pits are added in addition to data bits and ECC check bits, and a switching circuit that switches between each data bit and the spare bit, The configuration is such that the switching circuit is controlled to switch based on bit error information, and the data bit I in which the error has occurred is switched to a spare bit.

[Embodiment] FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a schematic explanatory diagram showing an example of a memory configuration.

In FIG. 1, 10 is a memory such as a main storage device,
In addition to the conventional configuration of a data length of 32 bits and a check bit of 7 bits, the memory configuration has a spare pit of 1 bit.

20 is an ECC circuit, 30 is a 1-bit error correction circuit, 4
0 is a selector circuit that designates a switching circuit (described later) based on error pit number information from the ECC circuit 20.

Further, 500 to 531 are switching circuits that respectively switch data 00 bit to data 31 bit to reserved bits according to the output from the selector circuit 40. Here, each switching circuit corresponds to the data bit and the inverted selector circuit 4.
The first AND gate circuit AN that requires two people to output 0 and
D1, a spare bit, and a second AND gate circuit AND2 which outputs the selector circuit 40 by two people.

Next, the operation of the hit error correction device having the above configuration will be explained.

A case will now be described in which the data bit MDI is defective and in an error state.

32 cut data (MDO~31) and check codes CO~C6 are read out from the memory 10, and the ECC circuit 20
, the ECC circuit 20 creates a syndrome from the input data, but at this time, if the MDI is in error, the syndrome is created indicating that the pit is in error and 1 is an error.

Based on this information, the ECC circuit 20 uses the correction port #
An instruction is issued to r30 to invert only MDI, and the read data DO to D31 are obtained as corrected correct data.

At this time, error bit number information is simultaneously sent to the selector 40 in ECC cycle #r20.

Based on this input information, the selector 40 selects 501 of the switching circuits 500 to 531 (MDI bit compatible).
Start up and switch to the spare MDSBY bit. In the case of FIG. 1, by setting only the output of the selector circuit 40 outputted to the switching circuit 5.01 to IIIGI+, the second AND gate circuit AND 2 is logically established; Instead of data bit MDI, spare bit MDSBY is switched and output.

Therefore, not only correct data can be obtained from the read data DO to D31, but also the memory circuit 10 can continue to be used as a circuit without defective bits.

Note that the present invention is not limited to the above embodiments,
Various modifications are possible within the scope of the invention.

[Effects of the Invention] As explained in 1-1 above, the present invention stores a spare bit in the memory f(iff), and when a 1-bit error occurs, switches the error bit to the spare bit, so that when a new 1-bit error occurs ( Even in the case of a total of 2 hit errors), the 1-bit error correction function J1 can be utilized, and even multiple hit errors can be corrected.

Furthermore, there is no need for quick maintenance work when a one-pitch error occurs.

Furthermore, in the case of data with a length of 32 bits, detection of 1 and 1 and 2 bits is possible if there is a check bit of 7 bits in length, but in actual memory circuits, it is possible to detect 1 and 2 bits with a positive check bit of 8 bits (1 byte). As a result, the length of 32+7 bits is used as 32+8=40. Therefore, there is also the advantage of making use of one unused bit.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a schematic explanatory drawing showing an example of a memory configuration corresponding to No. 11\l, and Fig. 3 is a block diagram for explaining a conventional system. be. 10: Memory 20: ECC circuit 30 error correction circuit 40: Selectors 500-531: Switching circuits corresponding to data 0-31, respectively MDO-MD31: Memory data bits DO-D31
: Corrected data bits CO to C6: Check code bits created by ECC circuit (ML) SBY: Memory spare (S'l'ND BY)
data bit

Claims (1)

[Claims] (1) A bit error correction device using an ECC circuit, comprising a memory configured to add spare bits in addition to data bits and ECC check bits, and a switching circuit that switches between each data bit and the spare bit, A bit error correction device characterized in that the switching circuit is switched and controlled based on 1-bit error information from the circuit, and a data bit in which an error has occurred is switched to a spare bit.