JPS56124193A - Error correction system - Google Patents

Error correction system

Info

Publication number
JPS56124193A
JPS56124193A JP2468280A JP2468280A JPS56124193A JP S56124193 A JPS56124193 A JP S56124193A JP 2468280 A JP2468280 A JP 2468280A JP 2468280 A JP2468280 A JP 2468280A JP S56124193 A JPS56124193 A JP S56124193A
Authority
JP
Japan
Prior art keywords
error
data
register
refresh
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2468280A
Other languages
Japanese (ja)
Inventor
Masateru Tagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2468280A priority Critical patent/JPS56124193A/en
Publication of JPS56124193A publication Critical patent/JPS56124193A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE:To obtain an error correction system where the access time is not delayed, by writing corrected data aa the refresh time after the address of data at the error detection time is stored in the error address register. CONSTITUTION:Data from memory 4 is returned directly through read data buffer register 5 without error correction at the normal read time. Meanwhile, data of this register 5 is applied to error detecting circuit 10; and if the error is detected, error presence/absence display register 14 is turned on, and the next refresh cycle is held. At the refresh time after that, the refresh address is switched to an address corresponding to error data which is stored in error address register 11, and the refresh mode is switched to the read modify write mode, and error data of memory 4 is written and corrected through error correcting circuit 6 and correct data register 13. Consequently, the error is corrected while the normal read is repeated, and the access time is not delayed.
JP2468280A 1980-02-29 1980-02-29 Error correction system Pending JPS56124193A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2468280A JPS56124193A (en) 1980-02-29 1980-02-29 Error correction system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2468280A JPS56124193A (en) 1980-02-29 1980-02-29 Error correction system

Publications (1)

Publication Number Publication Date
JPS56124193A true JPS56124193A (en) 1981-09-29

Family

ID=12144915

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2468280A Pending JPS56124193A (en) 1980-02-29 1980-02-29 Error correction system

Country Status (1)

Country Link
JP (1) JPS56124193A (en)

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