DE3686721D1 - Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist. - Google Patents

Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist.

Info

Publication number
DE3686721D1
DE3686721D1 DE8686430035T DE3686721T DE3686721D1 DE 3686721 D1 DE3686721 D1 DE 3686721D1 DE 8686430035 T DE8686430035 T DE 8686430035T DE 3686721 T DE3686721 T DE 3686721T DE 3686721 D1 DE3686721 D1 DE 3686721D1
Authority
DE
Germany
Prior art keywords
slope
layer
oxidiser
percentage
dry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686430035T
Other languages
English (en)
Inventor
Bernard Auda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3686721D1 publication Critical patent/DE3686721D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
DE8686430035T 1986-10-08 1986-10-08 Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist. Expired - Lifetime DE3686721D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP86430035A EP0263220B1 (de) 1986-10-08 1986-10-08 Verfahren zur Herstellung einer Kontaktöffnung mit gewünschter Schräge in einer zusammengesetzten Schicht, die mit Photoresist maskiert ist

Publications (1)

Publication Number Publication Date
DE3686721D1 true DE3686721D1 (de) 1992-10-15

Family

ID=8196403

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686430035T Expired - Lifetime DE3686721D1 (de) 1986-10-08 1986-10-08 Verfahren zur herstellung einer kontaktoeffnung mit gewuenschter schraege in einer zusammengesetzten schicht, die mit photoresist maskiert ist.

Country Status (4)

Country Link
US (1) US4814041A (de)
EP (1) EP0263220B1 (de)
JP (1) JPH0626205B2 (de)
DE (1) DE3686721D1 (de)

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US7056624B2 (en) * 2001-02-15 2006-06-06 Dai Nippon Printing Co., Ltd. Methods of manufacturing phase shift masks having etched substrate shifters with sidewalls rounded at top and bottom corners
KR100425100B1 (ko) * 2001-08-27 2004-03-30 엘지전자 주식회사 건식식각에 의한 그루브 제조방법 및 그를 이용한광통신용소자
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JP5446388B2 (ja) * 2009-03-31 2014-03-19 サンケン電気株式会社 集積化半導体装置の製造方法
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CN103779271B (zh) * 2012-10-26 2017-04-05 中微半导体设备(上海)有限公司 一种倒锥形轮廓刻蚀方法
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CN106946769B (zh) * 2017-04-16 2019-04-02 内蒙古佳瑞米精细化工有限公司 一种2-氟-5-三氟甲基吡啶的合成方法
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CN112928069B (zh) * 2021-02-05 2023-02-28 长鑫存储技术有限公司 半导体结构的制作方法及半导体结构

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Also Published As

Publication number Publication date
JPS63104338A (ja) 1988-05-09
US4814041A (en) 1989-03-21
JPH0626205B2 (ja) 1994-04-06
EP0263220B1 (de) 1992-09-09
EP0263220A1 (de) 1988-04-13

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