US6074957A - Methods of forming openings and methods of controlling the degree of taper of openings - Google Patents
Methods of forming openings and methods of controlling the degree of taper of openings Download PDFInfo
- Publication number
- US6074957A US6074957A US09/031,090 US3109098A US6074957A US 6074957 A US6074957 A US 6074957A US 3109098 A US3109098 A US 3109098A US 6074957 A US6074957 A US 6074957A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
Definitions
- This invention relates to methods of forming contact openings and to methods of controlling the degree of taper of contact openings.
- contact openings are often formed through insulative material for establishing electrical communication with the integrated circuitry.
- Such contact openings are typically subsequently filled with conductive material, such as a metal or polysilicon, whereby electrical communication is established with the integrated circuitry.
- Contact openings are often formed to be fairly narrow; and, it is desirable from a design standpoint to form the contact openings to have sidewalls which are as near vertical as possible. This helps to ensure that the contact area at the bottom of the contact opening is sufficiently large to desirably cover and/or expose conductive material with which electrical communication is desired.
- aspect ratios i.e. the height-to-width ratio
- of contact openings increase, it becomes increasingly important to ensure that the dimension of the bottom of the contact opening is sufficiently large to provide adequate coverage for conductive material which is subsequently formed therein.
- For narrow contact openings such is accomplished by maintaining the sidewalls of the contact opening as near vertical as possible.
- FIGS. 1 and 2 two exemplary contact opening etch profiles are indicated generally at 100, 100a respectively.
- FIG. 1 shows a substrate 102 with a layer of insulative material 104 formed thereover.
- a masking layer 106 such as photoresist is formed over insulative material 104 and is subsequently patterned to define a contact opening pattern.
- Contact opening 108 is etched using an etch which is highly selective relative to masking layer 106. Hence, while a desirably high level of selectivity ensures that masking layer 106 remains over the substrate, the subsequent etch profile is unsatisfactorily tapered.
- FIG. 2 shows a substrate 100a in which like numbers from FIG. 1 have been utilized with the suffix "a".
- a contact opening 108a is etched through layer 104a using an etch with a comparatively lower degree of selectivity relative to an overlying masking layer (not shown).
- the lower degree of selectivity results in a contact opening profile with a more desirable degree of taper.
- the overlying masking layer can be completely removed, thereby undesirably opening up other substrate features to etching.
- This invention arose out of concerns associated with providing methods of forming contact openings having sidewalls which are generally vertical within desired tolerances. This invention also arose out of concerns associated with providing methods for controlling the degree of taper of contact openings.
- a layer is first etched through a contact mask opening using a first set of etching conditions.
- the etching conditions provide a first degree of sidewall taper from vertical, if etching completely through the layer.
- the layer is second etched through the contact mask opening using a second set of etching conditions.
- the second set of etching conditions provide a second degree of sidewall taper from vertical, if etching completely through the layer.
- the second degree of sidewall taper is different from the first degree of taper.
- a material through which a contact opening is to be etched to a selected depth is formed over a substrate.
- a masking layer having an opening therein is formed over the material.
- the material is first etched through the opening with the first etch having a first selectivity relative to the masking layer.
- the material is second etched, with the second etch having a second selectivity relative to the masking layer which is greater than the first selectivity.
- the second degree of selectivity is achieved by modifying an etch parameter during the etching of the contact opening.
- FIG. 1 is a diagrammatic side sectional view of a semiconductor wafer fragment having a contact opening thereover which has been etched utilizing an etch which is highly selective relative to an overlying masking layer.
- FIG. 2 is a view which is similar to the FIG. 1 view, only one which shows a contact opening which has been etched using an etch with a low degree of selectivity relative to a previously-formed masking layer.
- FIG. 3 is a diagrammatic side sectional view of a semiconductor wafer fragment in process in accordance with one aspect of the invention.
- FIG. 4 is a view of the FIG. 3 wafer fragment at a different processing step.
- FIG. 5 is a view of the FIG. 3 wafer fragment at a different processing step.
- FIG. 6 is a view of a portion of a sidewall of a contact opening which is etched in accordance with one aspect of the invention.
- FIG. 7 is a graph which depicts taper angle versus step 1 etch depth.
- FIG. 8 is a graph which depicts contact area versus step 1 etch depth.
- a semiconductor wafer fragment in process is shown generally at 10 and comprises a semiconductive substrate 12.
- semiconductive substrate is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials).
- substrate refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
- substrate 12 has a diffusion region 13 formed therein with which electrical communication is desired.
- a layer 14 of material is formed over substrate 12 and through which a contact opening having a selected depth is to be etched.
- An exemplary material for layer 14 is an oxide material such as borophosphosilicate glass (BPSG) formed to an example thickness of 2.2 micron.
- BPSG borophosphosilicate glass
- layer 14 comprises a single layer of BPSG.
- Other materials and numbers of layers can, of course, be used.
- a masking layer 16 is formed over layer 14 and subsequently patterned to define a contact mask opening 18 which exposes a surface portion 20 of layer 14.
- An exemplary material for masking layer 16 is photoresist.
- material of layer 14 is first etched through contact mask opening 18 using a first set of etching conditions or parameters which collectively provide a first degree of sidewall taper from vertical were etching to occur completely through the layer.
- layer 14 is second etched using a second set of etching conditions or parameters which provide a second degree of sidewall taper from vertical were etching to occur completely through the layer.
- the second etching continues to proximate the depth selected for contact opening 22.
- the selected depth is one which is sufficient to reach diffusion region 13.
- the second etching can, however, be terminated before reaching the ultimate depth to which the contact opening is to be etched.
- the second degree of sidewall taper is different from the first degree of sidewall taper. Even more preferably, the first degree of sidewall taper is less than the second degree of sidewall taper.
- the first set of etching conditions are selected to provide a first degree of selectivity relative to masking layer 16.
- the etching conditions or parameters are changed to provide the second etch with a second selectivity relative to masking layer 16 which is greater than the first selectivity.
- the first and second etches of layer 14 are dry etches.
- a portion of a sidewall of contact opening 22 is indicated at 24. Such is displaced from a vertical line 25, or has a degree of taper from top-to-bottom away from vertical which defines an angle ⁇ , wherein ⁇ is preferably no greater than about 3°. Even more preferably, ⁇ is around 1.5°.
- FIGS. 7 and 8 two graphs are set forth which describe data measured in a reduction to practice example.
- a LAM TCP 9100 high density oxide etcher was utilized to form contact openings as described above.
- BPSG was utilized as the layer through which the contact opening was etched, and the selected desired depth of the contact opening was around 2 microns.
- the following etch conditions or parameters were utilized: 1050 Watts Source/1050 Watts Bias; 10 sccm C 2 HF 5 , 15 sccm CHF 3 , 5 sccm CH 2 F 2 , at 15 mTorr.
- the first set of etch conditions comprise a first ratio of carbon to fluorine sufficient to provide a first degree of selectivity relative to the masking layer, e.g. the photoresist.
- the second etch was conducted with the following etch conditions or parameters: 700 Watts Source/700 Watts Bias; 20 sccm C 2 HF 5 , 10 sccm CHF 3 , 10 sccm CH 2 F 2 at 20 mTorr.
- the second set of etch conditions comprise a second ratio of carbon to fluorine to provide a second degree of selectivity relative to the masking layer which is different, and preferably greater than the first degree of selectivity.
- the second ratio is lower than the first ratio.
- Table 1 below describes data associated with the first and second etches.
- the first and second columns designated as “T1" and “T2" respectively, are the respective times, in seconds, of the first and second etches.
- the "Depth” column describes the depth, in microns, of the ultimately-etched contact opening, e.g. the selected depth.
- the "S1 Depth” column describes the depth, in microns, at which the first etch was modified to the second etch.
- the "Taper Angle” column describes the angle of taper of the sidewalls of the ultimately-etched contact opening away from vertical.
- contact opening taper angle is plotted in degrees away from vertical, as a function of the depth at which the first etch was changed to the second etch.
- a plurality of data points are shown at A, B, C, D, E, F, and G.
- Each data point corresponds to an individual row in Table 1.
- data point G (last row in Table 1) describes a contact opening having a taper angle slightly larger than 1.5°.
- Such contact opening was formed, referring to Table 1, by conducting the first etch for 30 seconds, modifying the etch chemistry or parameters, and then conducting the second etch for 150 seconds. Such resulted in an intermediate switch point between etches of around 0.44 micron, for a resulting contact opening depth of around 2.6 micron.
- contact area at the bottom of the contact opening is plotted as a function of the depth at which the first etch was changed to the second etch for the same data points. Utilizing the same parameters or etch conditions as described above in connection with FIG. 7, the largest contact area observed appeared where the degree of taper away from vertical was the smallest, i.e. data point G. Such is desirable, as mentioned above, from the standpoint of opening up as much potential conductive contact area within desired tolerances.
- methods of the present invention enable a degree of contact opening taper to be controlled and selected. Such methods also provide for contact openings having generally vertical sidewalls which increase the contact area at the bottom of the contact opening.
Abstract
Description
TABLE 1 ______________________________________ T1 T2 Depth S1 Depth Taper Angle ______________________________________ (A) 1 150 2.3 0.015 3.005 (B) 5 145 2.2 0.073 2.434 (C) 10 140 2.3 0.147 2.434 (D) 15 135 2.3 0.220 2.148 (E) 20 130 2.3 0.293 2.005 (F) 40 110 2.2 0.587 2.148 (G) 30 150 2.6 0.440 1.575 ______________________________________
Claims (2)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/031,090 US6074957A (en) | 1998-02-26 | 1998-02-26 | Methods of forming openings and methods of controlling the degree of taper of openings |
US09/568,093 US6291359B1 (en) | 1998-02-26 | 2000-05-09 | Methods of forming openings and methods of controlling the degree of taper of openings |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/031,090 US6074957A (en) | 1998-02-26 | 1998-02-26 | Methods of forming openings and methods of controlling the degree of taper of openings |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/568,093 Continuation US6291359B1 (en) | 1998-02-26 | 2000-05-09 | Methods of forming openings and methods of controlling the degree of taper of openings |
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US6074957A true US6074957A (en) | 2000-06-13 |
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US09/031,090 Expired - Lifetime US6074957A (en) | 1998-02-26 | 1998-02-26 | Methods of forming openings and methods of controlling the degree of taper of openings |
US09/568,093 Expired - Lifetime US6291359B1 (en) | 1998-02-26 | 2000-05-09 | Methods of forming openings and methods of controlling the degree of taper of openings |
Family Applications After (1)
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US09/568,093 Expired - Lifetime US6291359B1 (en) | 1998-02-26 | 2000-05-09 | Methods of forming openings and methods of controlling the degree of taper of openings |
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Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6291359B1 (en) * | 1998-02-26 | 2001-09-18 | Micron Technology, Inc. | Methods of forming openings and methods of controlling the degree of taper of openings |
US6569774B1 (en) | 2000-08-31 | 2003-05-27 | Micron Technology, Inc. | Method to eliminate striations and surface roughness caused by dry etch |
US20030155328A1 (en) * | 2002-02-15 | 2003-08-21 | Huth Mark C. | Laser micromachining and methods and systems of same |
US6635335B1 (en) | 1999-06-29 | 2003-10-21 | Micron Technology, Inc. | Etching methods and apparatus and substrate assemblies produced therewith |
US20040226926A1 (en) * | 2003-05-13 | 2004-11-18 | Pollard Jeffrey R. | Laser micromachining systems |
US6921725B2 (en) | 2001-06-28 | 2005-07-26 | Micron Technology, Inc. | Etching of high aspect ratio structures |
US7754999B2 (en) | 2003-05-13 | 2010-07-13 | Hewlett-Packard Development Company, L.P. | Laser micromachining and methods of same |
US20140295668A1 (en) * | 2013-03-29 | 2014-10-02 | Tokyo Electron Limited | Reducing bowing bias in etching an oxide layer |
CN107706147A (en) * | 2017-10-18 | 2018-02-16 | 武汉新芯集成电路制造有限公司 | A kind of preparation method of vertical-type contact hole |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8153502B2 (en) * | 2006-05-16 | 2012-04-10 | Micron Technology, Inc. | Methods for filling trenches in a semiconductor material |
US20100331158A1 (en) * | 2009-06-30 | 2010-12-30 | Cmd Corporation | Method and Apparatus For Applying Closures To Pouches |
Citations (7)
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US4162185A (en) * | 1978-03-21 | 1979-07-24 | International Business Machines Corporation | Utilizing saturated and unsaturated halocarbon gases in plasma etching to increase etch of SiO2 relative to Si |
US4671849A (en) * | 1985-05-06 | 1987-06-09 | International Business Machines Corporation | Method for control of etch profile |
US4814041A (en) * | 1986-10-08 | 1989-03-21 | International Business Machines Corporation | Method of forming a via-hole having a desired slope in a photoresist masked composite insulating layer |
US5310454A (en) * | 1992-03-04 | 1994-05-10 | Kabushiki Kaisha Toshiba | Dry etching method |
US5420077A (en) * | 1990-06-29 | 1995-05-30 | Sharp Kabushiki Kaisha | Method for forming a wiring layer |
US5746884A (en) * | 1996-08-13 | 1998-05-05 | Advanced Micro Devices, Inc. | Fluted via formation for superior metal step coverage |
US5750441A (en) * | 1996-05-20 | 1998-05-12 | Micron Technology, Inc. | Mask having a tapered profile used during the formation of a semiconductor device |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US4807016A (en) * | 1985-07-15 | 1989-02-21 | Texas Instruments Incorporated | Dry etch of phosphosilicate glass with selectivity to undoped oxide |
US5021121A (en) * | 1990-02-16 | 1991-06-04 | Applied Materials, Inc. | Process for RIE etching silicon dioxide |
US6074957A (en) * | 1998-02-26 | 2000-06-13 | Micron Technology, Inc. | Methods of forming openings and methods of controlling the degree of taper of openings |
-
1998
- 1998-02-26 US US09/031,090 patent/US6074957A/en not_active Expired - Lifetime
-
2000
- 2000-05-09 US US09/568,093 patent/US6291359B1/en not_active Expired - Lifetime
Patent Citations (7)
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US4162185A (en) * | 1978-03-21 | 1979-07-24 | International Business Machines Corporation | Utilizing saturated and unsaturated halocarbon gases in plasma etching to increase etch of SiO2 relative to Si |
US4671849A (en) * | 1985-05-06 | 1987-06-09 | International Business Machines Corporation | Method for control of etch profile |
US4814041A (en) * | 1986-10-08 | 1989-03-21 | International Business Machines Corporation | Method of forming a via-hole having a desired slope in a photoresist masked composite insulating layer |
US5420077A (en) * | 1990-06-29 | 1995-05-30 | Sharp Kabushiki Kaisha | Method for forming a wiring layer |
US5310454A (en) * | 1992-03-04 | 1994-05-10 | Kabushiki Kaisha Toshiba | Dry etching method |
US5750441A (en) * | 1996-05-20 | 1998-05-12 | Micron Technology, Inc. | Mask having a tapered profile used during the formation of a semiconductor device |
US5746884A (en) * | 1996-08-13 | 1998-05-05 | Advanced Micro Devices, Inc. | Fluted via formation for superior metal step coverage |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6291359B1 (en) * | 1998-02-26 | 2001-09-18 | Micron Technology, Inc. | Methods of forming openings and methods of controlling the degree of taper of openings |
US20070077724A1 (en) * | 1999-06-29 | 2007-04-05 | Micron Technology, Inc. | Etching methods and apparatus and substrate assemblies produced therewith |
US6635335B1 (en) | 1999-06-29 | 2003-10-21 | Micron Technology, Inc. | Etching methods and apparatus and substrate assemblies produced therewith |
US6784111B2 (en) * | 1999-06-29 | 2004-08-31 | Micron Technology, Inc. | Etching methods and apparatus and substrate assemblies produced therewith |
US20040262263A1 (en) * | 1999-06-29 | 2004-12-30 | Micron Technology, Inc. | Etching methods and apparatus and substrate assemblies produced therewith |
US7125804B2 (en) | 1999-06-29 | 2006-10-24 | Micron Technology, Inc. | Etching methods and apparatus and substrate assemblies produced therewith |
US6569774B1 (en) | 2000-08-31 | 2003-05-27 | Micron Technology, Inc. | Method to eliminate striations and surface roughness caused by dry etch |
US20030162395A1 (en) * | 2000-08-31 | 2003-08-28 | Micron Technology, Inc. | Method to eliminate striations and surface roughness caused by dry etch |
US7153779B2 (en) | 2000-08-31 | 2006-12-26 | Micron Technology, Inc. | Method to eliminate striations and surface roughness caused by dry etch |
US7033954B2 (en) | 2001-06-28 | 2006-04-25 | Micron Technology, Inc. | Etching of high aspect ration structures |
US6921725B2 (en) | 2001-06-28 | 2005-07-26 | Micron Technology, Inc. | Etching of high aspect ratio structures |
US20060049156A1 (en) * | 2002-02-15 | 2006-03-09 | Michael Mulloy | Method of forming substrate for fluid ejection device |
US20030155328A1 (en) * | 2002-02-15 | 2003-08-21 | Huth Mark C. | Laser micromachining and methods and systems of same |
US8653410B2 (en) | 2002-02-15 | 2014-02-18 | Hewlett-Packard Development Company, L.P. | Method of forming substrate for fluid ejection device |
US6969822B2 (en) | 2003-05-13 | 2005-11-29 | Hewlett-Packard Development Company, L.P. | Laser micromachining systems |
US20040226926A1 (en) * | 2003-05-13 | 2004-11-18 | Pollard Jeffrey R. | Laser micromachining systems |
US7754999B2 (en) | 2003-05-13 | 2010-07-13 | Hewlett-Packard Development Company, L.P. | Laser micromachining and methods of same |
US20140295668A1 (en) * | 2013-03-29 | 2014-10-02 | Tokyo Electron Limited | Reducing bowing bias in etching an oxide layer |
US9165785B2 (en) * | 2013-03-29 | 2015-10-20 | Tokyo Electron Limited | Reducing bowing bias in etching an oxide layer |
CN107706147A (en) * | 2017-10-18 | 2018-02-16 | 武汉新芯集成电路制造有限公司 | A kind of preparation method of vertical-type contact hole |
CN107706147B (en) * | 2017-10-18 | 2020-05-12 | 武汉新芯集成电路制造有限公司 | Preparation method of vertical contact hole |
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